minor changes to GD32 core

rogerclarkmelbourne · rogerclarkmelbourne · commit 53ffab068b9d · 2015-08-31T21:55:28.000+10:00
diff --git a/GD32F1/cores/maple/libmaple/rcc_f1.c b/GD32F1/cores/maple/libmaple/rcc_f1.c
@@ -131,7 +131,7 @@ void rcc_configure_pll(rcc_pll_cfg *pll_cfg) {
 
     cfgr = RCC_BASE->CFGR;
     cfgr &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL);
-    cfgr |= pll_cfg->pllsrc | pll_mul;
+    cfgr |= pll_cfg->pllsrc | pll_mul;// | (0B10 << 22);
     RCC_BASE->CFGR = cfgr;
 }
 
diff --git a/GD32F1/variants/generic_gd32f103c/wirish/boards_setup.cpp b/GD32F1/variants/generic_gd32f103c/wirish/boards_setup.cpp
@@ -49,6 +49,7 @@
 // currently officially supports).
 #ifndef BOARD_RCC_PLLMUL
 #define BOARD_RCC_PLLMUL RCC_PLLMUL_10
+//#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
 #endif
 
 namespace wirish {

Original file line number	Diff line number	Diff line change
`@@ -131,7 +131,7 @@ void rcc_configure_pll(rcc_pll_cfg *pll_cfg) {`
`131`	`131`
`132`	`132`	`cfgr = RCC_BASE->CFGR;`
`133`	`133`	`cfgr &= ~(RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMUL);`
`134`		`- cfgr \|= pll_cfg->pllsrc \| pll_mul;`
	`134`	`+ cfgr \|= pll_cfg->pllsrc \| pll_mul;// \| (0B10 << 22);`
`135`	`135`	`RCC_BASE->CFGR = cfgr;`
`136`	`136`	`}`
`137`	`137`