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stevstrongstevstrong
committed
bring up in sync with master
1 parent 753d929 commit 832f102

5 files changed

Lines changed: 1 addition & 222 deletions

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‎STM32F4/cores/maple/libmaple/dmaF4.h‎

Lines changed: 0 additions & 73 deletions
Original file line numberDiff line numberDiff line change
@@ -85,12 +85,7 @@ typedef struct dma_reg_map {
8585
* Register bit definitions
8686
*/
8787

88-
<<<<<<< HEAD:STM32F4/cores/maple/libmaple/dmaF4.h
89-
/* Stream configuration register */
90-
91-
=======
9288
// Stream configuration register
93-
>>>>>>> refs/remotes/origin/master:STM32F4/cores/maple/libmaple/dmaF4.h
9489
#define DMA_CR_CH0 (0x0 << 25)
9590
#define DMA_CR_CH1 (0x1 << 25)
9691
#define DMA_CR_CH2 (0x2 << 25)
@@ -139,9 +134,6 @@ typedef struct dma_reg_map {
139134
#define DMA_CR_HTIE (0x1 << 3)
140135
#define DMA_CR_TEIE (0x1 << 2)
141136
#define DMA_CR_DMEIE (0x1 << 1)
142-
<<<<<<< HEAD:STM32F4/cores/maple/libmaple/dmaF4.h
143-
#define DMA_CR_EN (0x1)
144-
=======
145137
#define DMA_CR_EN (0x1 << 0)
146138

147139
// Device interrupt status register flags
@@ -170,7 +162,6 @@ typedef struct dma_reg_map {
170162
#define DMA_FCR_FTH_3_4 (0x2 << 0) // 3/4 full FIFO
171163
#define DMA_FCR_FTH_FULL (0x3 << 0) // full FIFO
172164

173-
>>>>>>> refs/remotes/origin/master:STM32F4/cores/maple/libmaple/dmaF4.h
174165

175166
typedef enum dma_channel {
176167
DMA_CH0 = DMA_CR_CH0, /**< Channel 0 */
@@ -182,21 +173,6 @@ typedef enum dma_channel {
182173
DMA_CH6 = DMA_CR_CH6, /**< Channel 6 */
183174
DMA_CH7 = DMA_CR_CH7, /**< Channel 7 */
184175
} dma_channel;
185-
<<<<<<< HEAD:STM32F4/cores/maple/libmaple/dmaF4.h
186-
187-
/* Device interrupt status register flags */
188-
189-
#define DMA_ISR_TCIF (1 << 5)
190-
#define DMA_ISR_HTIF (1 << 4)
191-
#define DMA_ISR_TEIF (1 << 3)
192-
#define DMA_ISR_DMEIF (1 << 2)
193-
#define DMA_ISR_FEIF (1 << 0)
194-
195-
/*
196-
* Devices
197-
*/
198-
=======
199-
>>>>>>> refs/remotes/origin/master:STM32F4/cores/maple/libmaple/dmaF4.h
200176

201177
/** Encapsulates state related to a DMA channel interrupt. */
202178
typedef struct dma_handler_config {
@@ -218,29 +194,6 @@ typedef struct dma_dev {
218194
/*
219195
* Devices
220196
*/
221-
<<<<<<< HEAD:STM32F4/cores/maple/libmaple/dmaF4.h
222-
223-
extern void dma_init(dma_dev *dev);
224-
225-
/** Flags for DMA transfer configuration. */
226-
typedef enum dma_mode_flags {
227-
DMA_MEM_BUF_0 = DMA_CR_CT0, /**< Current memory target buffer 0 */
228-
DMA_MEM_BUF_1 = DMA_CR_CT1, /**< Current memory target buffer 1 */
229-
DMA_DBL_BUF_MODE = DMA_CR_DBM, /**< Current memory double buffer mode */
230-
DMA_PINC_OFFSET = DMA_CR_PINCOS, /**< Peripheral increment offset size */
231-
DMA_MINC_MODE = DMA_CR_MINC, /**< Memory increment mode */
232-
DMA_PINC_MODE = DMA_CR_PINC, /**< Peripheral increment mode */
233-
DMA_CIRC_MODE = DMA_CR_CIRC, /**< Memory Circular mode */
234-
DMA_FROM_PER = DMA_CR_DIR_P2M, /**< Read from memory to peripheral */
235-
DMA_FROM_MEM = DMA_CR_DIR_M2P, /**< Read from memory to peripheral */
236-
DMA_MEM_TO_MEM = DMA_CR_DIR_M2M, /**< Read from memory to memory */
237-
DMA_PERIF_CTRL = DMA_CR_PFCTRL, /**< Peripheral flow controller */
238-
DMA_PRIO_MEDIUM = DMA_CR_PL_MEDIUM, /**< Medium priority */
239-
DMA_PRIO_HIGH = DMA_CR_PL_HIGH, /**< High priority */
240-
DMA_PRIO_VERY_HIGH = DMA_CR_PL_VERY_HIGH, /**< Very high priority */
241-
DMA_TRNS_CMPLT = DMA_CR_TCIE, /**< Interrupt on transfer completion */
242-
DMA_TRNS_HALF = DMA_CR_HTIE, /**< Interrupt on half-transfer */
243-
=======
244197
extern dma_dev *DMA1;
245198
extern dma_dev *DMA2;
246199

@@ -262,22 +215,15 @@ typedef enum dma_mode_flags {
262215
DMA_PRIO_VERY_HIGH = DMA_CR_PL_VERY_HIGH, /**< Very high priority */
263216
DMA_TRNS_CMPLT = DMA_CR_TCIE, /**< Interrupt on transfer completion */
264217
DMA_TRNS_HALF = DMA_CR_HTIE, /**< Interrupt on half-transfer */
265-
>>>>>>> refs/remotes/origin/master:STM32F4/cores/maple/libmaple/dmaF4.h
266218
DMA_TRNS_ERR = DMA_CR_TEIE, /**< Interrupt on transfer error */
267219
DMA_DIR_MODE_ERR = DMA_CR_DMEIE /**< Interrupt on direct mode error */
268220
} dma_mode_flags;
269221

270222
// Source and destination transfer sizes.
271223
typedef enum dma_xfer_size {
272-
<<<<<<< HEAD:STM32F4/cores/maple/libmaple/dmaF4.h
273-
DMA_SIZE_8BITS = ( DMA_CR_MSIZE_8BITS|DMA_CR_PSIZE_8BITS ), /**< 8-bit transfers */
274-
DMA_SIZE_16BITS = (DMA_CR_MSIZE_16BITS|DMA_CR_PSIZE_16BITS), /**< 16-bit transfers */
275-
DMA_SIZE_32BITS = (DMA_CR_MSIZE_32BITS|DMA_CR_PSIZE_32BITS) /**< 32-bit transfers */
276-
=======
277224
DMA_SIZE_8BITS = ( DMA_CR_MSIZE_8BITS|DMA_CR_PSIZE_8BITS ), // 8-bit transfers
278225
DMA_SIZE_16BITS = (DMA_CR_MSIZE_16BITS|DMA_CR_PSIZE_16BITS), // 16-bit transfers
279226
DMA_SIZE_32BITS = (DMA_CR_MSIZE_32BITS|DMA_CR_PSIZE_32BITS) // 32-bit transfers
280-
>>>>>>> refs/remotes/origin/master:STM32F4/cores/maple/libmaple/dmaF4.h
281227
} dma_xfer_size;
282228

283229
// Source and destination burst sizes.
@@ -312,22 +258,14 @@ static inline void dma_setup_transfer(dma_dev *dev,
312258
__io void *peripheral_address,
313259
__io void *memory_address0,
314260
__io void *memory_address1,
315-
<<<<<<< HEAD:STM32F4/cores/maple/libmaple/dmaF4.h
316-
uint32 flags) {
317-
=======
318261
uint32 flags)
319262
{
320-
>>>>>>> refs/remotes/origin/master:STM32F4/cores/maple/libmaple/dmaF4.h
321263
dev->regs->STREAM[stream].CR &= ~DMA_CR_EN; // disable
322264
while( (dev->regs->STREAM[stream].CR)&DMA_CR_EN ); // wait till enable bit is cleared
323265
dev->regs->STREAM[stream].PAR = (uint32)peripheral_address;
324266
dev->regs->STREAM[stream].M0AR = (uint32)memory_address0;
325267
dev->regs->STREAM[stream].M1AR = (uint32)memory_address1;
326-
<<<<<<< HEAD:STM32F4/cores/maple/libmaple/dmaF4.h
327-
dev->regs->STREAM[stream].CR = ((flags|channel|trx_size) & 0x0feffffe); // mask out reserved and enable
328-
=======
329268
dev->regs->STREAM[stream].CR = (uint32)((flags|channel|trx_size) & 0x0feffffe); // mask out reserved and enable
330-
>>>>>>> refs/remotes/origin/master:STM32F4/cores/maple/libmaple/dmaF4.h
331269
}
332270

333271
static inline void dma_set_num_transfers(dma_dev *dev, dma_stream stream, uint16 num_transfers)
@@ -340,12 +278,6 @@ static inline void dma_set_fifo_flags(dma_dev *dev, dma_stream stream, uint8 fif
340278
dev->regs->STREAM[stream].FCR = (uint32)(fifo_flags & 0x87); // mask out reserved bits
341279
}
342280

343-
static inline void dma_set_fifo_flags(dma_dev *dev,
344-
dma_stream stream,
345-
uint8 fifo_flags) {
346-
dev->regs->STREAM[stream].FCR = fifo_flags & 0x87; // mask out reserved bits
347-
}
348-
349281
void dma_attach_interrupt(dma_dev *dev,
350282
dma_stream stream,
351283
void (*handler)(void));
@@ -357,14 +289,9 @@ static inline void dma_enable(dma_dev *dev, dma_stream stream)
357289
dev->regs->STREAM[stream].CR |= (uint32)DMA_CR_EN;
358290
}
359291

360-
<<<<<<< HEAD:STM32F4/cores/maple/libmaple/dmaF4.h
361-
static inline void dma_disable(dma_dev *dev, dma_stream stream) {
362-
dev->regs->STREAM[stream].CR &= ~DMA_CR_EN;
363-
=======
364292
static inline void dma_disable(dma_dev *dev, dma_stream stream)
365293
{
366294
dev->regs->STREAM[stream].CR &= (uint32)(~DMA_CR_EN);
367-
>>>>>>> refs/remotes/origin/master:STM32F4/cores/maple/libmaple/dmaF4.h
368295
while (dev->regs->STREAM[stream].CR & DMA_CR_EN); // wait till EN bit is reset, see AN4031, chapter 4.1
369296
}
370297

‎STM32F4/cores/maple/libmaple/fsmc.c‎

Lines changed: 0 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -37,62 +37,6 @@
3737
/**
3838
* Configure FSMC GPIOs for use with LCDs.
3939
*/
40-
<<<<<<< HEAD
41-
void fsmc_sram_init_gpios(void) {
42-
/* Data lines... */
43-
gpio_set_mode(PD0, GPIO_AF_OUTPUT_PP);
44-
gpio_set_mode(PD1, GPIO_AF_OUTPUT_PP);
45-
gpio_set_mode(PD8, GPIO_AF_OUTPUT_PP);
46-
gpio_set_mode(PD9, GPIO_AF_OUTPUT_PP);
47-
gpio_set_mode(PD10, GPIO_AF_OUTPUT_PP);
48-
gpio_set_mode(PD14, GPIO_AF_OUTPUT_PP);
49-
gpio_set_mode(PD15, GPIO_AF_OUTPUT_PP);
50-
gpio_set_mode(PE7, GPIO_AF_OUTPUT_PP);
51-
gpio_set_mode(PE8, GPIO_AF_OUTPUT_PP);
52-
gpio_set_mode(PE9, GPIO_AF_OUTPUT_PP);
53-
gpio_set_mode(PE10, GPIO_AF_OUTPUT_PP);
54-
gpio_set_mode(PE11, GPIO_AF_OUTPUT_PP);
55-
gpio_set_mode(PE12, GPIO_AF_OUTPUT_PP);
56-
gpio_set_mode(PE13, GPIO_AF_OUTPUT_PP);
57-
gpio_set_mode(PE14, GPIO_AF_OUTPUT_PP);
58-
gpio_set_mode(PE15, GPIO_AF_OUTPUT_PP);
59-
60-
/* Address lines... */
61-
gpio_set_mode(PD11, GPIO_AF_OUTPUT_PP);
62-
gpio_set_mode(PD12, GPIO_AF_OUTPUT_PP);
63-
gpio_set_mode(PD13, GPIO_AF_OUTPUT_PP);
64-
#if 0 // not available on LQFP package
65-
gpio_set_mode(GPIOF, 0, GPIO_AF_OUTPUT_PP);
66-
gpio_set_mode(GPIOF, 1, GPIO_AF_OUTPUT_PP);
67-
gpio_set_mode(GPIOF, 2, GPIO_AF_OUTPUT_PP);
68-
gpio_set_mode(GPIOF, 3, GPIO_AF_OUTPUT_PP);
69-
gpio_set_mode(GPIOF, 4, GPIO_AF_OUTPUT_PP);
70-
gpio_set_mode(GPIOF, 5, GPIO_AF_OUTPUT_PP);
71-
gpio_set_mode(GPIOF, 12, GPIO_AF_OUTPUT_PP);
72-
gpio_set_mode(GPIOF, 13, GPIO_AF_OUTPUT_PP);
73-
gpio_set_mode(GPIOF, 14, GPIO_AF_OUTPUT_PP);
74-
gpio_set_mode(GPIOF, 15, GPIO_AF_OUTPUT_PP);
75-
gpio_set_mode(GPIOG, 0, GPIO_AF_OUTPUT_PP);
76-
gpio_set_mode(GPIOG, 1, GPIO_AF_OUTPUT_PP);
77-
gpio_set_mode(GPIOG, 2, GPIO_AF_OUTPUT_PP);
78-
gpio_set_mode(GPIOG, 3, GPIO_AF_OUTPUT_PP);
79-
gpio_set_mode(GPIOG, 4, GPIO_AF_OUTPUT_PP);
80-
gpio_set_mode(GPIOG, 5, GPIO_AF_OUTPUT_PP);
81-
#endif // not available on LQFP package
82-
/* And control lines... */
83-
gpio_set_mode(PD4, GPIO_AF_OUTPUT_PP); // NOE
84-
gpio_set_mode(PD5, GPIO_AF_OUTPUT_PP); // NWE
85-
86-
gpio_set_mode(PD7, GPIO_AF_OUTPUT_PP); // NE1
87-
#if 0 // not available on LQFP package
88-
gpio_set_mode(GPIOG, 9, GPIO_AF_OUTPUT_PP); // NE2
89-
gpio_set_mode(GPIOG, 10, GPIO_AF_OUTPUT_PP); // NE3
90-
gpio_set_mode(GPIOG, 12, GPIO_AF_OUTPUT_PP); // NE4
91-
#endif // not available on LQFP package
92-
93-
gpio_set_mode(PE0, GPIO_AF_OUTPUT_PP); // NBL0
94-
gpio_set_mode(PE1, GPIO_AF_OUTPUT_PP); // NBL1
95-
=======
9640

9741
void fsmc_init(void) {
9842
rcc_clk_enable(RCC_FSMC);
@@ -137,7 +81,6 @@ void fsmc_lcd_init(void)
13781
fsmc_nor_psram_set_BTR(FSMC_NOR_PSRAM1_BASE, val);
13882
// enable FSCM
13983
fsmc_nor_psram_bank_enable(FSMC_NOR_PSRAM1_BASE);
140-
>>>>>>> refs/remotes/origin/master
14184
}
14285

14386

‎STM32F4/libraries/SPI/src/SPI.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -460,6 +460,7 @@ uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length
460460
while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream) & DMA_ISR_TCIF)==0 ) {// wait for completion flag to be set
461461
if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
462462
}
463+
463464
while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
464465
while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
465466
// software disable sequence, see AN4031, chapter 4.1

‎STM32F4/system/libmaple/Arduino.h~HEAD‎

Lines changed: 0 additions & 46 deletions
This file was deleted.

‎STM32F4/system/libmaple/Arduino.h~refs_remotes_origin_master‎

Lines changed: 0 additions & 46 deletions
This file was deleted.

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