Merge branch 'fix_spi_ss'

Author: rogerclarkmelbourne

STM32F1/cores/maple/libmaple/gpio_f1.c

@@ -138,6 +138,23 @@ void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode) {
     }
 }
 
+gpio_pin_mode gpio_get_mode(gpio_dev *dev, uint8 pin) {
+    gpio_reg_map *regs = dev->regs;
+    __io uint32 *cr = &regs->CRL + (pin >> 3);
+    uint32 shift = (pin & 0x7) * 4;
+    uint32 tmp = *cr;
+
+	uint32 crMode = (*cr>>shift) & 0x0F;
+	
+	// could be pull up or pull down. Nee to check the ODR
+	if (crMode==GPIO_INPUT_PD && ((regs->ODR >> pin) & 0x01) !=0 )
+	{
+		crMode = GPIO_INPUT_PU;
+	}
+	
+    return(crMode);
+}
+
 /*
  * AFIO
  */

STM32F1/cores/maple/libmaple/spi_f1.c

@@ -63,7 +63,7 @@ void spi_config_gpios(spi_dev *ignored,
                       uint8 miso_bit,
                       uint8 mosi_bit) {
     if (as_master) {
-        gpio_set_mode(nss_dev, nss_bit, GPIO_AF_OUTPUT_PP);
+     //   gpio_set_mode(nss_dev, nss_bit, GPIO_AF_OUTPUT_PP);// Roger Clark. Commented out, so that NSS can be driven as a normal GPIO pin during SPI use
         gpio_set_mode(comm_dev, sck_bit, GPIO_AF_OUTPUT_PP);
         gpio_set_mode(comm_dev, miso_bit, GPIO_INPUT_FLOATING);
         gpio_set_mode(comm_dev, mosi_bit, GPIO_AF_OUTPUT_PP);

STM32F1/libraries/SPI/src/SPI.cpp

@@ -119,10 +119,7 @@ SPIClass::SPIClass(uint32 spi_num) {
  */
 
 void SPIClass::begin(void) {
-    if (dataMode >= 4) {
-        ASSERT(0);
-        return;
-    }
+	
     uint32 flags = ((bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | SPI_DFF_8_BIT | SPI_SW_SLAVE | SPI_SOFT_SS);
     spi_init(spi_d);
     configure_gpios(spi_d, 1);

STM32F1/system/libmaple/include/libmaple/gpio.h

@@ -71,7 +71,7 @@ void gpio_init(gpio_dev *dev);
 void gpio_init_all(void);
 /* TODO flags argument version? */
 void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode);
-
+gpio_pin_mode gpio_get_mode(gpio_dev *dev, uint8 pin);
 /**
  * @brief Get a GPIO port's corresponding EXTI port configuration.
  * @param dev GPIO port whose exti_cfg to return.