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GD32F1 Core. Added enhancements from @victor_pv to disable USB prescaler and re-enable so that the USB prescaler can be changed by the core during startup
1 parent d79f346 commit b96247a

4 files changed

Lines changed: 25 additions & 0 deletions

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GD32F1/cores/maple/libmaple/rcc_f1.c

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@@ -162,3 +162,12 @@ void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider) {
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};
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rcc_do_set_prescaler(masks, prescaler, divider);
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}
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void rcc_clk_disable(rcc_clk_id id) {
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static __io uint32* enable_regs[] = {
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[APB1] = &RCC_BASE->APB1ENR,
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[APB2] = &RCC_BASE->APB2ENR,
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[AHB] = &RCC_BASE->AHBENR,
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};
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rcc_do_clk_disable(enable_regs, id);
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}

GD32F1/system/libmaple/include/libmaple/rcc.h

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@@ -169,6 +169,12 @@ static inline void rcc_disable_css() {
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RCC_BASE->CR &= ~RCC_CR_CSSON;
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}
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/**
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* @brief Turn off the clock line on a peripheral
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* @param id Clock ID of the peripheral to turn on.
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*/
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extern void rcc_clk_disable(rcc_clk_id id);
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#ifdef __cplusplus
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} // extern "C"
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#endif

GD32F1/system/libmaple/rcc_private.h

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@@ -64,4 +64,11 @@ static inline void rcc_do_set_prescaler(const uint32 *masks,
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RCC_BASE->CFGR = cfgr;
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}
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static inline void rcc_do_clk_disable(__io uint32** enable_regs,
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rcc_clk_id id) {
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__io uint32 *enable_reg = enable_regs[rcc_dev_clk(id)];
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uint8 line_num = rcc_dev_table[id].line_num;
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bb_peri_set_bit(enable_reg, line_num, 0);
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}
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#endif

GD32F1/variants/generic_gd32f103c/wirish/boards_setup.cpp

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@@ -79,12 +79,15 @@ namespace wirish {
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rcc_set_prescaler(RCC_PRESCALER_AHB, RCC_AHB_SYSCLK_DIV_1);
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rcc_set_prescaler(RCC_PRESCALER_APB1, RCC_APB1_HCLK_DIV_2);
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rcc_set_prescaler(RCC_PRESCALER_APB2, RCC_APB2_HCLK_DIV_1);
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rcc_clk_disable(RCC_USB);
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#if F_CPU == 120000000
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rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_2_5);
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#elif F_CPU == 96000000
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rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_2);
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#elif F_CPU == 72000000
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rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);
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#elif F_CPU == 48000000
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rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);
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#endif
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}
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