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rogerclarkmelbournerogerclarkmelbourne
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Merge branch 'development'
2 parents 268d920 + d0ed194 commit ba5d405

12 files changed

Lines changed: 103 additions & 50 deletions

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‎STM32F1/boards.txt‎

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -125,10 +125,8 @@ nucleo_f103rb.upload.altID=1
125125
nucleo_f103rb.upload.auto_reset=true
126126

127127
nucleo_f103rb.build.mcu=cortex-m3
128-
nucleo_f103rb.build.f_cpu=72000000L
129-
nucleo_f103rb.build.board=STM_NUCLEU_F103RB
128+
nucleo_f103rb.build.board=STM_NUCLEO_F103RB
130129
nucleo_f103rb.build.core=maple
131-
nucleo_f103rb.build.extra_flags=-DMCU_STM32F103RB -mthumb -march=armv7-m -D__STM32F1__
132130
nucleo_f103rb.build.ldscript=ld/jtag.ld
133131
nucleo_f103rb.build.variant=nucleo_f103rb
134132
nucleo_f103rb.build.variant_system_lib=libmaple.a
@@ -139,6 +137,16 @@ nucleo_f103rb.build.error_led_pin=1
139137
nucleo_f103rb.build.gcc_ver=gcc-arm-none-eabi-4.8.3-2014q1
140138
nucleo_f103rb.build.vect=VECT_TAB_ADDR=0x8000000
141139

140+
## internal oscillator (HSI), running at 64 MHz
141+
nucleo_f103rb.menu.device_variant.NucleoF103_HSI=Nucleo F103 @ 64 MHz
142+
nucleo_f103rb.menu.device_variant.NucleoF103_HSI.build.f_cpu=64000000L
143+
nucleo_f103rb.menu.device_variant.NucleoF103_HSI.build.extra_flags=-DMCU_STM32F103RB -mthumb -march=armv7-m -D__STM32F1__
144+
145+
## external crystal (HSE), running at 72 MHz
146+
nucleo_f103rb.menu.device_variant.NucleoF103_HSE=Nucleo F103 @ 72 MHz w/ crystal
147+
nucleo_f103rb.menu.device_variant.NucleoF103_HSE.build.f_cpu=72000000L
148+
nucleo_f103rb.menu.device_variant.NucleoF103_HSE.build.extra_flags=-DNUCLEO_HSE_CRYSTAL -DMCU_STM32F103RB -mthumb -march=armv7-m -D__STM32F1__
149+
142150
###################### Generic STM32F103C ########################################
143151

144152
genericSTM32F103C.name=Generic STM32F103C series

‎STM32F1/cores/maple/HardwareSerial.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -141,11 +141,11 @@ void HardwareSerial::begin(uint32 baud, uint8_t config)
141141

142142
disable_timer_if_necessary(txi->timer_device, txi->timer_channel);
143143

144+
usart_init(this->usart_device);
144145
usart_config_gpios_async(this->usart_device,
145146
rxi->gpio_device, rxi->gpio_bit,
146147
txi->gpio_device, txi->gpio_bit,
147148
config);
148-
usart_init(this->usart_device);
149149
usart_set_baud_rate(this->usart_device, USART_USE_PCLK, baud);
150150
usart_enable(this->usart_device);
151151
}

‎STM32F1/cores/maple/HardwareSerial.h‎

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -83,22 +83,25 @@ struct usart_dev;
8383
*/
8484
// Define config for Serial.begin(baud, config);
8585
// Note. STM32 doesn't support as many different Serial modes as AVR or SAM cores.
86+
// The word legth bit M must be set when using parity bit.
8687

8788
#define SERIAL_8N1 0B00000000
8889
#define SERIAL_8N2 0B00100000
8990
#define SERIAL_9N1 0B00001000
9091
#define SERIAL_9N2 0B00101000
9192

92-
#define SERIAL_8E1 0B00000010
93-
#define SERIAL_8E2 0B00100010
93+
#define SERIAL_8E1 0B00001010
94+
#define SERIAL_8E2 0B00101010
95+
/* not supported:
9496
#define SERIAL_9E1 0B00001010
9597
#define SERIAL_9E2 0B00101010
96-
97-
#define SERIAL_8O1 0B00000011
98-
#define SERIAL_8O2 0B00100011
98+
*/
99+
#define SERIAL_8O1 0B00001011
100+
#define SERIAL_8O2 0B00101011
101+
/* not supported:
99102
#define SERIAL_9O1 0B00001011
100103
#define SERIAL_9O2 0B00101011
101-
104+
*/
102105

103106
/* Roger Clark
104107
* Moved macros from hardwareSerial.cpp

‎STM32F1/cores/maple/libmaple/usart_f1.c‎

Lines changed: 13 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -108,13 +108,14 @@ void usart_config_gpios_async(usart_dev *udev,
108108
gpio_set_mode(rx_dev, rx, GPIO_INPUT_FLOATING);
109109
gpio_set_mode(tx_dev, tx, GPIO_AF_OUTPUT_PP);
110110
/*
111-
112111
CR1 bit 12 Word length 0=8 1=9
113112
CR1 bit 11 wake (default value is 0) we can safely set this value to 0 (zero) each time
114113
CR1 bit 10 parity enable (1 = enabled)
115114
CR1 bit 9 Parity selection 0 = Even 1 = Odd
116115
CR2 bits 13 and 12 00 = 1 01 = 0.5 10 = 2 11 = 1.5
117116
Not all USARTs support 1.5 or 0.5 bits so its best to avoid them.
117+
When parity enabled the word length must be increased (CR1 bit 12 set).
118+
Word length of 9 bit with parity is not supported.
118119
CR2 CR1
119120
0B00 0000
120121
0B10 0000
@@ -136,21 +137,19 @@ Not all USARTs support 1.5 or 0.5 bits so its best to avoid them.
136137
#define SERIAL_9N1 0B 0000 1000
137138
#define SERIAL_9N2 0B 0010 1000
138139
139-
#define SERIAL_8E1 0B 0000 0010
140-
#define SERIAL_8E2 0B 0010 0010
141-
#define SERIAL_9E1 0B 0000 1010
142-
#define SERIAL_9E2 0B 0010 1010
143-
144-
#define SERIAL_8O1 0B 0000 0011
145-
#define SERIAL_8O2 0B 0010 0011
146-
#define SERIAL_9O1 0B 0000 1011
147-
#define SERIAL_9O2 0B 0010 1011
148-
149-
*/
140+
#define SERIAL_8E1 0B 0000 1010
141+
#define SERIAL_8E2 0B 0010 1010
142+
//#define SERIAL_9E1 0B 0000 1010
143+
//#define SERIAL_9E2 0B 0010 1010
150144
145+
#define SERIAL_8O1 0B 0000 1011
146+
#define SERIAL_8O2 0B 0010 1011
147+
//#define SERIAL_9O1 0B 0000 1011
148+
//#define SERIAL_9O2 0B 0010 1011
149+
*/
151150

152-
udev->regs->CR1 = udev->regs->CR1 ^ ((udev->regs->CR1 ^ (flags&0x0F)<<9 ) & 0B0001111000000000);
153-
udev->regs->CR2 = udev->regs->CR2 ^ ((udev->regs->CR2 ^ (flags&0xF0)<<8 ) & 0B0011000000000000);
151+
udev->regs->CR1 = (udev->regs->CR1 & 0B1110000111111111) | ((uint32_t)(flags&0x0F)<<9);
152+
udev->regs->CR2 = (udev->regs->CR2 & 0B1100111111111111) | ((uint32_t)(flags&0x30)<<8);
154153
}
155154

156155
void usart_set_baud_rate(usart_dev *dev, uint32 clock_speed, uint32 baud) {

‎STM32F1/cores/maple/usb_serial.cpp‎

Lines changed: 11 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -126,12 +126,17 @@ size_t n = 0;
126126
}
127127

128128

129-
if (sent == USB_CDCACM_TX_EPSIZE) {
130-
while (usb_cdcacm_is_transmitting() != 0) {
131-
}
132-
/* flush out to avoid having the pc wait for more data */
133-
usb_cdcacm_tx(NULL, 0);
134-
}
129+
#if 0
130+
// this code leads to a serious performance drop and appears to be
131+
// unnecessary - everything seems to work fine without, -jcw, 2015-11-05
132+
// see http://stm32duino.com/posting.php?mode=quote&f=3&p=7746
133+
if (sent == USB_CDCACM_TX_EPSIZE) {
134+
while (usb_cdcacm_is_transmitting() != 0) {
135+
}
136+
/* flush out to avoid having the pc wait for more data */
137+
usb_cdcacm_tx(NULL, 0);
138+
}
139+
#endif
135140
return n;
136141
}
137142

‎STM32F1/cores/maple/wirish_time.cpp‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -34,10 +34,9 @@
3434
#include <libmaple/delay.h>
3535

3636
void delay(unsigned long ms) {
37-
uint32 i;
38-
for (i = 0; i < ms; i++) {
39-
delayMicroseconds(1000);
40-
}
37+
uint32 start = millis();
38+
while (millis() - start < ms)
39+
;
4140
}
4241

4342
void delayMicroseconds(uint32 us) {

‎STM32F1/libraries/SPI/src/SPI.cpp‎

Lines changed: 17 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -141,16 +141,19 @@ SPIClass::SPIClass(uint32 spi_num) {
141141
/*
142142
* Set up/tear down
143143
*/
144+
void SPIClass::updateSettings(void) {
145+
uint32 flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | SPI_DFF_8_BIT | SPI_SW_SLAVE | SPI_SOFT_SS);
146+
#ifdef SPI_DEBUG
147+
Serial.print("spi_master_enable("); Serial.print(_currentSetting->clockDivider); Serial.print(","); Serial.print(_currentSetting->dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
148+
#endif
149+
spi_master_enable(_currentSetting->spi_d, (spi_baud_rate)_currentSetting->clockDivider, (spi_mode)_currentSetting->dataMode, flags);
150+
}
144151

145152
void SPIClass::begin(void) {
146153

147-
uint32 flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | SPI_DFF_8_BIT | SPI_SW_SLAVE | SPI_SOFT_SS);
148154
spi_init(_currentSetting->spi_d);
149155
configure_gpios(_currentSetting->spi_d, 1);
150-
#ifdef SPI_DEBUG
151-
Serial.print("spi_master_enable("); Serial.print(_currentSetting->clockDivider); Serial.print(","); Serial.print(_currentSetting->dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
152-
#endif
153-
spi_master_enable(_currentSetting->spi_d, (spi_baud_rate)_currentSetting->clockDivider, (spi_mode)_currentSetting->dataMode, flags);
156+
updateSettings();
154157
}
155158

156159
void SPIClass::beginSlave(void) {
@@ -192,7 +195,7 @@ void SPIClass::setClockDivider(uint32_t clockDivider)
192195
Serial.print("Clock divider set to "); Serial.println(clockDivider);
193196
#endif
194197
_currentSetting->clockDivider = clockDivider;
195-
this->begin();
198+
updateSettings();
196199
}
197200

198201
void SPIClass::setBitOrder(BitOrder bitOrder)
@@ -201,7 +204,7 @@ void SPIClass::setBitOrder(BitOrder bitOrder)
201204
Serial.print("Bit order set to "); Serial.println(bitOrder);
202205
#endif
203206
_currentSetting->bitOrder = bitOrder;
204-
this->begin();
207+
updateSettings();
205208
}
206209

207210
/* Victor Perez. Added to test changing datasize from 8 to 16 bit modes on the fly.
@@ -250,8 +253,8 @@ If someone finds this is not the case or sees a logic error with this let me kno
250253
Serial.print("Data mode set to "); Serial.println(dataMode);
251254
#endif
252255
_currentSetting->dataMode = dataMode;
253-
this->begin();
254-
}
256+
updateSettings();
257+
}
255258

256259

257260
void SPIClass::beginTransaction(uint8_t pin, SPISettings settings)
@@ -266,7 +269,6 @@ void SPIClass::beginTransaction(uint8_t pin, SPISettings settings)
266269
setDataMode(settings.dataMode);
267270
setClockDivider(determine_baud_rate(_currentSetting->spi_d, settings.clock));
268271
begin();
269-
270272
}
271273

272274
void SPIClass::endTransaction(void)
@@ -346,13 +348,16 @@ void SPIClass::write(const uint8 *data, uint32 length) {
346348
}
347349
while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "4. After writing the last data item into the SPI_DR register, wait until TXE=1 ..."
348350
while (spi_is_busy(_currentSetting->spi_d) != 0); // "... then wait until BSY=0, this indicates that the transmission of the last data is complete."
351+
// taken from SdSpiSTM32F1.cpp - Victor's lib, and adapted to support device selection
352+
if (spi_is_rx_nonempty(_currentSetting->spi_d)) {
353+
uint8_t b = spi_rx_reg(_currentSetting->spi_d);
354+
}
349355
}
350356

351357
uint8 SPIClass::transfer(uint8 byte) const {
352-
uint8 b;
353358
spi_tx_reg(_currentSetting->spi_d, byte); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
354359
while (spi_is_rx_nonempty(_currentSetting->spi_d) == 0); // "4. Wait until RXNE=1 ..."
355-
b = spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
360+
uint8 b = spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
356361
while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
357362
while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
358363
return b;

‎STM32F1/libraries/SPI/src/SPI.h‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -88,8 +88,8 @@
8888
#endif
8989

9090
// PC13 or PA4
91-
//#define BOARD_SPI_DEFAULT_SS PA4
92-
#define BOARD_SPI_DEFAULT_SS PC13
91+
#define BOARD_SPI_DEFAULT_SS PA4
92+
//#define BOARD_SPI_DEFAULT_SS PC13
9393

9494
#define SPI_MODE0 SPI_MODE_0
9595
#define SPI_MODE1 SPI_MODE_1
@@ -375,6 +375,7 @@ class SPIClass {
375375
SPISettings _settings[BOARD_NR_SPI];
376376
SPISettings *_currentSetting;
377377

378+
void updateSettings(void);
378379
/*
379380
spi_dev *spi_d;
380381
uint8_t _SSPin;

‎STM32F1/system/libmaple/stm32f1/include/series/adc.h‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -87,8 +87,24 @@ extern const struct adc_dev *ADC3;
8787
#define ADC_CR2_DMA (1U << ADC_CR2_DMA_BIT)
8888
#define ADC_CR2_ALIGN (1U << ADC_CR2_ALIGN_BIT)
8989
#define ADC_CR2_JEXTSEL 0x7000
90+
#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12)
91+
#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12)
92+
#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x2 << 12)
93+
#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x3 << 12)
94+
#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x4 << 12)
95+
#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x5 << 12)
96+
#define ADC_CR2_JEXTSEL_EXTI15 (0x6 << 12)
97+
#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12)
9098
#define ADC_CR2_JEXTTRIG (1U << ADC_CR2_JEXTTRIG_BIT)
9199
#define ADC_CR2_EXTSEL 0xE0000
100+
#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 17)
101+
#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 17)
102+
#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17)
103+
#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 17)
104+
#define ADC_CR2_EXTSEL_TIM3_TRGO (0x4 << 17)
105+
#define ADC_CR2_EXTSEL_TIM4_CC4 (0x5 << 17)
106+
#define ADC_CR2_EXTSEL_EXTI11 (0x6 << 17)
107+
#define ADC_CR2_EXTSEL_SWSTART (0x7 << 17)
92108
#define ADC_CR2_EXTTRIG (1U << ADC_CR2_EXTTRIG_BIT)
93109
#define ADC_CR2_JSWSTART (1U << ADC_CR2_JSWSTART_BIT)
94110
#define ADC_CR2_SWSTART (1U << ADC_CR2_SWSTART_BIT)

‎STM32F1/variants/nucleo_f103rb/wirish/boards.cpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -121,10 +121,12 @@ static void setup_clocks(void) {
121121
// readiness interrupts.
122122
RCC_BASE->CIR = 0x00000000;
123123

124+
#if NUCLEO_HSE_CRYSTAL
124125
// Enable HSE, and wait until it's ready.
125126
rcc_turn_on_clk(RCC_CLK_HSE);
126127
while (!rcc_is_clk_ready(RCC_CLK_HSE))
127128
;
129+
#endif
128130

129131
// Configure AHBx, APBx, etc. prescalers and the main PLL.
130132
wirish::priv::board_setup_clock_prescalers();

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