Slight changes

edogaldo · edogaldo · commit d353dd30226d · 2016-07-19T12:56:11.000+02:00
diff --git a/STM32F1/cores/maple/libmaple/usart.c b/STM32F1/cores/maple/libmaple/usart.c
@@ -105,7 +105,7 @@ uint32 usart_tx(usart_dev *dev, const uint8 *buf, uint32 len) {
         else
             break;
     }
-    if (rb_full_count(dev->wb) > 0) {
+    if (!rb_is_empty(dev->wb)) {
         regs->CR1 |= USART_CR1_TXEIE;
     }
     return txed;
diff --git a/STM32F1/system/libmaple/usart_private.h b/STM32F1/system/libmaple/usart_private.h
@@ -55,8 +55,9 @@ static inline __always_inline void usart_irq(ring_buffer *rb, ring_buffer *wb, u
     }
     /* TXE signifies readiness to send a byte to DR. */
     if ((regs->CR1 & USART_CR1_TXEIE) && (regs->SR & USART_SR_TXE)) {
-        regs->DR=rb_remove(wb);
-        if (rb_is_empty(wb))
+        if (!rb_is_empty(wb))
+            regs->DR=rb_remove(wb);
+        else
             regs->CR1 &= ~((uint32)USART_CR1_TXEIE); // disable TXEIE
     }
 }

Original file line number	Diff line number	Diff line change
`@@ -105,7 +105,7 @@ uint32 usart_tx(usart_dev dev, const uint8 buf, uint32 len) {`
`105`	`105`	`else`
`106`	`106`	`break;`
`107`	`107`	`}`
`108`		`- if (rb_full_count(dev->wb) > 0) {`
	`108`	`+ if (!rb_is_empty(dev->wb)) {`
`109`	`109`	`regs->CR1 \|= USART_CR1_TXEIE;`
`110`	`110`	`}`
`111`	`111`	`return txed;`
Original file line number	Diff line number	Diff line change
`@@ -55,8 +55,9 @@ static inline __always_inline void usart_irq(ring_buffer rb, ring_buffer wb, u`
`55`	`55`	`}`
`56`	`56`	`/* TXE signifies readiness to send a byte to DR. */`
`57`	`57`	`if ((regs->CR1 & USART_CR1_TXEIE) && (regs->SR & USART_SR_TXE)) {`
`58`		`- regs->DR=rb_remove(wb);`
`59`		`- if (rb_is_empty(wb))`
	`58`	`+ if (!rb_is_empty(wb))`
	`59`	`+ regs->DR=rb_remove(wb);`
	`60`	`+ else`
`60`	`61`	`regs->CR1 &= ~((uint32)USART_CR1_TXEIE); // disable TXEIE`
`61`	`62`	`}`
`62`	`63`	`}`