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Merge branch 'master' of https://github.com/stevstrong/Arduino_STM32 into stevstrong-master
2 parents 1fc436e + b81d7b7 commit e48ff38

3 files changed

Lines changed: 34 additions & 12 deletions

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STM32F1/libraries/SPI/src/SPI.cpp

Lines changed: 17 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -141,16 +141,19 @@ SPIClass::SPIClass(uint32 spi_num) {
141141
/*
142142
* Set up/tear down
143143
*/
144+
void SPIClass::updateSettings(void) {
145+
uint32 flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | SPI_DFF_8_BIT | SPI_SW_SLAVE | SPI_SOFT_SS);
146+
#ifdef SPI_DEBUG
147+
Serial.print("spi_master_enable("); Serial.print(_currentSetting->clockDivider); Serial.print(","); Serial.print(_currentSetting->dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
148+
#endif
149+
spi_master_enable(_currentSetting->spi_d, (spi_baud_rate)_currentSetting->clockDivider, (spi_mode)_currentSetting->dataMode, flags);
150+
}
144151

145152
void SPIClass::begin(void) {
146153

147-
uint32 flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | SPI_DFF_8_BIT | SPI_SW_SLAVE | SPI_SOFT_SS);
148154
spi_init(_currentSetting->spi_d);
149155
configure_gpios(_currentSetting->spi_d, 1);
150-
#ifdef SPI_DEBUG
151-
Serial.print("spi_master_enable("); Serial.print(_currentSetting->clockDivider); Serial.print(","); Serial.print(_currentSetting->dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
152-
#endif
153-
spi_master_enable(_currentSetting->spi_d, (spi_baud_rate)_currentSetting->clockDivider, (spi_mode)_currentSetting->dataMode, flags);
156+
updateSettings();
154157
}
155158

156159
void SPIClass::beginSlave(void) {
@@ -192,7 +195,7 @@ void SPIClass::setClockDivider(uint32_t clockDivider)
192195
Serial.print("Clock divider set to "); Serial.println(clockDivider);
193196
#endif
194197
_currentSetting->clockDivider = clockDivider;
195-
this->begin();
198+
updateSettings();
196199
}
197200

198201
void SPIClass::setBitOrder(BitOrder bitOrder)
@@ -201,7 +204,7 @@ void SPIClass::setBitOrder(BitOrder bitOrder)
201204
Serial.print("Bit order set to "); Serial.println(bitOrder);
202205
#endif
203206
_currentSetting->bitOrder = bitOrder;
204-
this->begin();
207+
updateSettings();
205208
}
206209

207210
/* Victor Perez. Added to test changing datasize from 8 to 16 bit modes on the fly.
@@ -250,8 +253,8 @@ If someone finds this is not the case or sees a logic error with this let me kno
250253
Serial.print("Data mode set to "); Serial.println(dataMode);
251254
#endif
252255
_currentSetting->dataMode = dataMode;
253-
this->begin();
254-
}
256+
updateSettings();
257+
}
255258

256259

257260
void SPIClass::beginTransaction(uint8_t pin, SPISettings settings)
@@ -266,7 +269,6 @@ void SPIClass::beginTransaction(uint8_t pin, SPISettings settings)
266269
setDataMode(settings.dataMode);
267270
setClockDivider(determine_baud_rate(_currentSetting->spi_d, settings.clock));
268271
begin();
269-
270272
}
271273

272274
void SPIClass::endTransaction(void)
@@ -346,13 +348,16 @@ void SPIClass::write(const uint8 *data, uint32 length) {
346348
}
347349
while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "4. After writing the last data item into the SPI_DR register, wait until TXE=1 ..."
348350
while (spi_is_busy(_currentSetting->spi_d) != 0); // "... then wait until BSY=0, this indicates that the transmission of the last data is complete."
351+
// taken from SdSpiSTM32F1.cpp - Victor's lib, and adapted to support device selection
352+
if (spi_is_rx_nonempty(_currentSetting->spi_d)) {
353+
uint8_t b = spi_rx_reg(_currentSetting->spi_d);
354+
}
349355
}
350356

351357
uint8 SPIClass::transfer(uint8 byte) const {
352-
uint8 b;
353358
spi_tx_reg(_currentSetting->spi_d, byte); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
354359
while (spi_is_rx_nonempty(_currentSetting->spi_d) == 0); // "4. Wait until RXNE=1 ..."
355-
b = spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
360+
uint8 b = spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
356361
while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
357362
while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
358363
return b;

STM32F1/libraries/SPI/src/SPI.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -375,6 +375,7 @@ class SPIClass {
375375
SPISettings _settings[BOARD_NR_SPI];
376376
SPISettings *_currentSetting;
377377

378+
void updateSettings(void);
378379
/*
379380
spi_dev *spi_d;
380381
uint8_t _SSPin;

STM32F1/system/libmaple/stm32f1/include/series/adc.h

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -87,8 +87,24 @@ extern const struct adc_dev *ADC3;
8787
#define ADC_CR2_DMA (1U << ADC_CR2_DMA_BIT)
8888
#define ADC_CR2_ALIGN (1U << ADC_CR2_ALIGN_BIT)
8989
#define ADC_CR2_JEXTSEL 0x7000
90+
#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12)
91+
#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12)
92+
#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x2 << 12)
93+
#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x3 << 12)
94+
#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x4 << 12)
95+
#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x5 << 12)
96+
#define ADC_CR2_JEXTSEL_EXTI15 (0x6 << 12)
97+
#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12)
9098
#define ADC_CR2_JEXTTRIG (1U << ADC_CR2_JEXTTRIG_BIT)
9199
#define ADC_CR2_EXTSEL 0xE0000
100+
#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 17)
101+
#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 17)
102+
#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17)
103+
#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 17)
104+
#define ADC_CR2_EXTSEL_TIM3_TRGO (0x4 << 17)
105+
#define ADC_CR2_EXTSEL_TIM4_CC4 (0x5 << 17)
106+
#define ADC_CR2_EXTSEL_EXTI11 (0x6 << 17)
107+
#define ADC_CR2_EXTSEL_SWSTART (0x7 << 17)
92108
#define ADC_CR2_EXTTRIG (1U << ADC_CR2_EXTTRIG_BIT)
93109
#define ADC_CR2_JSWSTART (1U << ADC_CR2_JSWSTART_BIT)
94110
#define ADC_CR2_SWSTART (1U << ADC_CR2_SWSTART_BIT)

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