121121 * line may be shared with another timer. For example, the timer 1
122122 * update interrupt shares an IRQ line with the timer 10 interrupt on
123123 * STM32F1 (XL-density), STM32F2, and STM32F4. */
124- static __always_inline void dispatch_single_irq (timer_dev * dev ,
124+ static inline __always_inline void dispatch_single_irq (timer_dev * dev ,
125125 timer_interrupt_id iid ,
126126 uint32 irq_mask ) {
127127 timer_bas_reg_map * regs = (dev -> regs ).bas ;
@@ -145,15 +145,15 @@ static __always_inline void dispatch_single_irq(timer_dev *dev,
145145 } \
146146 } while (0)
147147
148- static __always_inline void dispatch_adv_brk (timer_dev * dev ) {
148+ static inline __always_inline void dispatch_adv_brk (timer_dev * dev ) {
149149 dispatch_single_irq (dev , TIMER_BREAK_INTERRUPT , TIMER_SR_BIF );
150150}
151151
152- static __always_inline void dispatch_adv_up (timer_dev * dev ) {
152+ static inline __always_inline void dispatch_adv_up (timer_dev * dev ) {
153153 dispatch_single_irq (dev , TIMER_UPDATE_INTERRUPT , TIMER_SR_UIF );
154154}
155155
156- static __always_inline void dispatch_adv_trg_com (timer_dev * dev ) {
156+ static inline __always_inline void dispatch_adv_trg_com (timer_dev * dev ) {
157157 timer_adv_reg_map * regs = (dev -> regs ).adv ;
158158 uint32 dsr = regs -> DIER & regs -> SR ;
159159 void (* * hs )(void ) = dev -> handlers ;
@@ -168,7 +168,7 @@ static __always_inline void dispatch_adv_trg_com(timer_dev *dev) {
168168 regs -> SR &= ~handled ;
169169}
170170
171- static __always_inline void dispatch_adv_cc (timer_dev * dev ) {
171+ static inline __always_inline void dispatch_adv_cc (timer_dev * dev ) {
172172 timer_adv_reg_map * regs = (dev -> regs ).adv ;
173173 uint32 dsr = regs -> DIER & regs -> SR ;
174174 void (* * hs )(void ) = dev -> handlers ;
@@ -182,7 +182,7 @@ static __always_inline void dispatch_adv_cc(timer_dev *dev) {
182182 regs -> SR &= ~handled ;
183183}
184184
185- static __always_inline void dispatch_general (timer_dev * dev ) {
185+ static inline __always_inline void dispatch_general (timer_dev * dev ) {
186186 timer_gen_reg_map * regs = (dev -> regs ).gen ;
187187 uint32 dsr = regs -> DIER & regs -> SR ;
188188 void (* * hs )(void ) = dev -> handlers ;
@@ -200,7 +200,7 @@ static __always_inline void dispatch_general(timer_dev *dev) {
200200
201201/* On F1 (XL-density), F2, and F4, TIM9 and TIM12 are restricted
202202 * general-purpose timers with update, CC1, CC2, and TRG interrupts. */
203- static __always_inline void dispatch_tim_9_12 (timer_dev * dev ) {
203+ static inline __always_inline void dispatch_tim_9_12 (timer_dev * dev ) {
204204 timer_gen_reg_map * regs = (dev -> regs ).gen ;
205205 uint32 dsr = regs -> DIER & regs -> SR ;
206206 void (* * hs )(void ) = dev -> handlers ;
@@ -216,7 +216,7 @@ static __always_inline void dispatch_tim_9_12(timer_dev *dev) {
216216
217217/* On F1 (XL-density), F2, and F4, timers 10, 11, 13, and 14 are
218218 * restricted general-purpose timers with update and CC1 interrupts. */
219- static __always_inline void dispatch_tim_10_11_13_14 (timer_dev * dev ) {
219+ static inline __always_inline void dispatch_tim_10_11_13_14 (timer_dev * dev ) {
220220 timer_gen_reg_map * regs = (dev -> regs ).gen ;
221221 uint32 dsr = regs -> DIER & regs -> SR ;
222222 void (* * hs )(void ) = dev -> handlers ;
@@ -228,7 +228,7 @@ static __always_inline void dispatch_tim_10_11_13_14(timer_dev *dev) {
228228 regs -> SR &= ~handled ;
229229}
230230
231- static __always_inline void dispatch_basic (timer_dev * dev ) {
231+ static inline __always_inline void dispatch_basic (timer_dev * dev ) {
232232 dispatch_single_irq (dev , TIMER_UPDATE_INTERRUPT , TIMER_SR_UIF );
233233}
234234
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