From ddee0b614f56f6f1d055c7bbe69044205e78ec85 Mon Sep 17 00:00:00 2001 From: Jens Reidel Date: Tue, 26 Aug 2025 15:29:11 +0200 Subject: [PATCH] fix(pci): capabilities are always little-endian See https://docs.oasis-open.org/virtio/virtio/v1.2/cs01/virtio-v1.2-cs01.html#x1-1240004 "This virtio structure capability uses little-endian format" Signed-off-by: Jens Reidel --- src/pci.rs | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/pci.rs b/src/pci.rs index e48073a..8b1617f 100644 --- a/src/pci.rs +++ b/src/pci.rs @@ -119,7 +119,7 @@ pub struct Cap { impl Cap { pub fn read(addr: PciCapabilityAddress, access: impl ConfigRegionAccess) -> Option { let data = unsafe { access.read(addr.address, addr.offset) }; - let [cap_vndr, _cap_next, cap_len, _cfg_type] = data.to_ne_bytes(); + let [cap_vndr, _cap_next, cap_len, _cfg_type] = data.to_le_bytes(); if cap_vndr != 0x09 { return None; @@ -136,6 +136,8 @@ impl Cap { unsafe { access.read(addr.address, addr.offset + 12) }, ]; + let data: [u32; 4] = data.map(u32::from_le); + let this = unsafe { mem::transmute::<[u32; 4], Self>(data) }; Some(this)