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[FMV] Add support for more features #469

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21 changes: 21 additions & 0 deletions main/acle.md
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Expand Up @@ -3135,6 +3135,14 @@ The following table lists the architectures feature mapping for AArch64.
| `FEAT_SME_F16F16` | sme-f16f16 | ```ID_AA64SMFR0_EL1.F16F16 == 0b1``` |
| `FEAT_SME_F8F16` | sme-f8f16 | ```ID_AA64SMFR0_EL1.F8F16 == 0b1``` |
| `FEAT_SME_MOP4` | sme-mop4 | ```ID_AA64SMFR0_EL1.SMOP4 == 0b1``` |
| `FEAT_LSE2` | lse2 | ```ID_AA64MMFR2_EL1.AT >= 0b0001``` |

@mgabka mgabka Oct 16, 2026

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I am wondering if we should drop this feature for now. Do you have a use case for it?

@Lukacma Lukacma Oct 16, 2026

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Yes this feature is used to allow STP and LDP instructions to be used for 128-bit atomics.

@AlfieRichardsArm AlfieRichardsArm Oct 19, 2026

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LSE2 is not something modeled in GCC architecture flags so this would only be a dispatch feature for us, there would be no code gen change.

I would probably lean towards not including it as a personal preference.

@Lukacma Lukacma Oct 20, 2026

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So how does GCC work for 128-bit atomics ? It never makes use of STP and LDP even if present or is the LSE2 enabled by other flag ?

@AlfieRichardsArm AlfieRichardsArm Oct 20, 2026

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We talked about it a bit internally and it turns out we use ifuncs in libatomic, so that's a pretty clear argument that we should do this. We need to look into adding a march flag in GCC as well.

My next comment goes doubly so then, I think it is unlikely we will be able to do the work required for lse2 at this point.

@Lukacma Lukacma Oct 20, 2026

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Sorry I am not sure I quite understood you comment. It seems like you are suggesting that at some point supporting lse2 codegen will be necessary by GCC ? If that's the case, isn't it the argument for multiversioning this feature so users will be able to make use of that codegen using FMV ? I understand you cannot support it now, but LLVM can and since FMV is versioned you could just advertise older version to users so they don't expect GCC support for these and bump it once you add it. Or am I missing smth ?

@AlfieRichardsArm AlfieRichardsArm Oct 20, 2026

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Yes sorry I was unclear. That's what I mean. I was incorrect previously and I agree there is a case for LSE2 GCC (and we should add march flags for it)

But as this will be difficult in GCC I would prefer to have the FMV suport integer be incremented for this PR so we can differentiate to users if the previous FMV features make GCC 17 but LSE2 does not.

| `FEAT_SVE_B16B16` | sve-b16b16 | ```ID_AA64ZFR0_EL1.B16B16 >= 0b0001```|
| `FEAT_SME_B16B16` | sme-b16b16 | ```ID_AA64SMFR0_EL1.B16B16 == 0b1``` |
| `FEAT_LSE128` | lse128 | ```ID_AA64ISAR0_EL1.Atomic >= 0b0011``` |
| `FEAT_CMPBR` | cmpbr | ```ID_AA64ISAR2_EL1.CSSC >= 0b0010``` |
| `FEAT_FPRCVT` | fprcvt | ```ID_AA64ISAR3_EL1.FPRCVT >= 0b0001``` |
| `FEAT_LSFE` | lsfe | ```ID_AA64ISAR3_EL1.LSFE >= 0b0001``` |
| `FEAT_SME_TMOP` | sme-tmop | ```ID_AA64SMFR0_EL1.STMOP == 0b1``` |

The tables are sorted by priority, starting from features of lowest priority ending with features of highest priority.

Expand Down Expand Up @@ -3229,6 +3237,14 @@ unless otherwise specified.
| sme-f16f16 | 202690 |
| sme-f8f16 | 202690 |
| sme-mop4 | 202690 |
| lse2 | 202690 |

@AlfieRichardsArm AlfieRichardsArm Oct 19, 2026

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I think it would be safer to bump the version number for these. There's a possibility the previous ones make GCC 17 but these dont (depending on how much time I have).

| sve-b16b16 | 202690 |
| sme-b16b16 | 202690 |
| lse128 | 202690 |
| cmpbr | 202690 |
| fprcvt | 202690 |
| lsfe | 202690 |
| sme-tmop | 202690 |

### Dependencies

Expand Down Expand Up @@ -3298,6 +3314,11 @@ The following table lists the feature dependencies for AArch64.
| sme-f16f16 | sme2 |
| sme-f8f16 | sme2, fp8 |
| sme-mop4 | sme2 |
| sme-b16b16 | sme2, sve-b16b16 |
| lse128 | lse |
| fprcvt | fp |
| lsfe | fp |
| sme-tmop | sme2 |

### Selection

Expand Down
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