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fix(bb): size Pippenger MSM arena for the non-GLV mid-band#24249

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fix(bb): size Pippenger MSM arena for the non-GLV mid-band#24249
AztecBot wants to merge 1 commit into
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cb/pippenger-arena-midband-fix

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@AztecBot AztecBot commented Jun 23, 2026

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Problem

UltraHonk bb prove intermittently aborts in CI with:

libc++abi: terminating due to uncaught exception of type std::runtime_error:
Assertion failed: (aligned_local + bytes <= bound)
  Left   : 4123456
  Right  : 3699643

The assertion is MsmArena::bump_alloc's BB_ASSERT_LTE(aligned_local + bytes, bound) in scalar_multiplication_fast.cpp. It is not OOM — the per-MSM scratch arena was sized smaller than the live allocator consumes.

Root cause

compute_arena_bytes_for_msm sizes the arena from the conservative full-bit schedule (NUM_BITS = FULL_NUM_BITS = 254 for non-GLV). The live path (pippenger_round_parallel) then shrinks the budget to effective_num_bits = the observed max scalar MSB, which can make choose_window_bits pick a smaller window_bitsmore windows ⇒ a larger Zone S than the full-bit pre-size.

The sizer already has a defensive sweep that takes the max arena footprint across every bit budget, but it was gated if (use_glv || n_input >= 2^17). That left the non-GLV mid-band (GLV_SMALL_N_THRESHOLD < n_input < 2^17, i.e. 8192 < n < 131072 natively) sized for the full-bit schedule only. simple_shield's commitment MSM is ~28,696 points — non-GLV, squarely in that gap — so a witness whose scalars drive a smaller effective_num_bits overflows the arena.

It's intermittent because it needs both a runner core-count that yields the heavier schedule (this run reported 8 threads) and witness data whose max scalar MSB lands in the trigger band (~224–250). Both vary per run/PR, so it isn't tied to any particular PR.

Fix

Make the defensive bit-budget sweep unconditional. use_glv || n_input > GLV_SMALL_N_THRESHOLD is true for every MSM that reaches this point, so the sweep now covers GLV and all non-GLV sizes. It only ever grows the arena when a shrunk-bit layout genuinely needs more, so the common full-bit-dominated case stays tight. Arena sizing is scratch memory only — no effect on VKs or proof output.

Test

Added MidBandArenaSizerCoversAllEffectiveNumBits, which drives the module's own arena-fit simulator across the non-GLV mid-band × every effective_num_bits at 8 threads. It fails on the pre-fix sizer (under-counts at n=28,696 for effective_num_bits 224–248, among others) and passes with the fix. Full ScalarMultiplication* suite (110 tests, incl. real-MSM correctness and the small-scalar band test) passes.

@AztecBot AztecBot added ci-barretenberg Run all barretenberg/cpp checks. ci-draft Run CI on draft PRs. claudebox Owned by claudebox. it can push to this PR. labels Jun 23, 2026
AztecBot added a commit that referenced this pull request Jun 23, 2026
@iakovenkos iakovenkos changed the base branch from merge-train/barretenberg to next June 23, 2026 21:46
@AztecBot AztecBot force-pushed the cb/pippenger-arena-midband-fix branch from 7a3edd3 to 00761bd Compare June 23, 2026 21:50
@iakovenkos iakovenkos removed ci-barretenberg Run all barretenberg/cpp checks. ci-draft Run CI on draft PRs. labels Jun 23, 2026
@iakovenkos iakovenkos marked this pull request as ready for review June 23, 2026 21:55
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