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Implemented IRStatement to Instruction conversion
1 parent 88fe213 commit 8d5eba4

1 file changed

Lines changed: 115 additions & 51 deletions

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‎src/main/kotlin/deep/decaf/low/amd64/LowIRClasses.kt‎

Lines changed: 115 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
package deep.decaf.low.amd64
22

33
import deep.decaf.ir.*
4+
import java.lang.IllegalStateException
45
import java.util.*
56

67
fun getUUID(): String = UUID.randomUUID().toString().replace("-", "")
@@ -240,114 +241,114 @@ data class Program(
240241
)
241242

242243
fun irExprToLow(expr: IRExpr): List<Instruction> {
243-
val statements = mutableListOf<Instruction>()
244+
val instructions = mutableListOf<Instruction>()
244245

245246
fun traverse(expr: IRExpr): Location {
246247
return when (expr) {
247248
is IRIntLiteral -> ImmediateVal(expr.lit)
248249
is IRBoolLiteral -> ImmediateVal(if (expr.lit) 1 else 0)
249250
is IRMethodCallExpr -> {
250251
val argLocations = expr.argList.map { traverse(it) }
251-
argLocations.forEach { statements.add(PushInstruction(it)) }
252-
statements.add(CallInstruction(expr.name))
252+
argLocations.forEach { instructions.add(PushInstruction(it)) }
253+
instructions.add(CallInstruction(expr.name))
253254
for (i in 1..expr.argList.size) {
254-
statements.add(PopInstruction(null))
255+
instructions.add(PopInstruction(null))
255256
}
256257
Register.returnRegister()
257258
}
258259
is IRCallOutExpr -> TODO()
259260
is IRBinOpExpr -> {
260261
val leftLocation = traverse(expr.left)
261262
val rightLocation = traverse(expr.right)
262-
statements.add(MoveInstruction(leftLocation, Register.r10()))
263-
statements.add(MoveInstruction(rightLocation, Register.r11()))
263+
instructions.add(MoveInstruction(leftLocation, Register.r10()))
264+
instructions.add(MoveInstruction(rightLocation, Register.r11()))
264265
when (expr.op) {
265266
BinOp.ADD -> {
266-
statements.add(AddInstruction(Register.r11(), Register.r10()))
267+
instructions.add(AddInstruction(Register.r11(), Register.r10()))
267268
val tmp = Label(getUUID())
268-
statements.add(MoveInstruction(Register.r10(), tmp))
269+
instructions.add(MoveInstruction(Register.r10(), tmp))
269270
tmp
270271
}
271272
BinOp.SUBTRACT -> {
272-
statements.add(SubInstruction(Register.r11(), Register.r10()))
273+
instructions.add(SubInstruction(Register.r11(), Register.r10()))
273274
val tmp = Label(getUUID())
274-
statements.add(MoveInstruction(Register.r10(), tmp))
275+
instructions.add(MoveInstruction(Register.r10(), tmp))
275276
tmp
276277
}
277278
BinOp.MULTIPLY -> {
278-
statements.add(IMulInstruction(Register.r11(), Register.r10()))
279+
instructions.add(IMulInstruction(Register.r11(), Register.r10()))
279280
val tmp = Label(getUUID())
280-
statements.add(MoveInstruction(Register.r10(), tmp))
281+
instructions.add(MoveInstruction(Register.r10(), tmp))
281282
tmp
282283
}
283284
BinOp.DIVIDE -> {
284-
statements.add(MoveInstruction(Register.r10(), Register.rax()))
285-
statements.add(SignedExtendInstruction)
286-
statements.add(IDivInstruction(Register.r11()))
285+
instructions.add(MoveInstruction(Register.r10(), Register.rax()))
286+
instructions.add(SignedExtendInstruction)
287+
instructions.add(IDivInstruction(Register.r11()))
287288
val tmp = Label(getUUID())
288-
statements.add(MoveInstruction(Register.rax(), tmp))
289+
instructions.add(MoveInstruction(Register.rax(), tmp))
289290
tmp
290291
}
291292
BinOp.REMAINDER -> {
292-
statements.add(MoveInstruction(Register.r10(), Register.rax()))
293-
statements.add(SignedExtendInstruction)
294-
statements.add(IDivInstruction(Register.r11()))
293+
instructions.add(MoveInstruction(Register.r10(), Register.rax()))
294+
instructions.add(SignedExtendInstruction)
295+
instructions.add(IDivInstruction(Register.r11()))
295296
val tmp = Label(getUUID())
296-
statements.add(MoveInstruction(Register.rdx(), tmp))
297+
instructions.add(MoveInstruction(Register.rdx(), tmp))
297298
tmp
298299
}
299300
BinOp.LESS -> {
300-
statements.add(CmpInstruction(Register.r11(), Register.r10()))
301-
statements.add(SetInstruction(SetType.SETL, Register.r10b()))
301+
instructions.add(CmpInstruction(Register.r11(), Register.r10()))
302+
instructions.add(SetInstruction(SetType.SETL, Register.r10b()))
302303
val tmp = Label(getUUID())
303-
statements.add(MoveInstruction(Register.r10(), tmp))
304+
instructions.add(MoveInstruction(Register.r10(), tmp))
304305
tmp
305306
}
306307
BinOp.MORE -> {
307-
statements.add(CmpInstruction(Register.r11(), Register.r10()))
308-
statements.add(SetInstruction(SetType.SETG, Register.r10b()))
308+
instructions.add(CmpInstruction(Register.r11(), Register.r10()))
309+
instructions.add(SetInstruction(SetType.SETG, Register.r10b()))
309310
val tmp = Label(getUUID())
310-
statements.add(MoveInstruction(Register.r10(), tmp))
311+
instructions.add(MoveInstruction(Register.r10(), tmp))
311312
tmp
312313
}
313314
BinOp.LESS_OR_EQ -> {
314-
statements.add(CmpInstruction(Register.r11(), Register.r10()))
315-
statements.add(SetInstruction(SetType.SETLE, Register.r10b()))
315+
instructions.add(CmpInstruction(Register.r11(), Register.r10()))
316+
instructions.add(SetInstruction(SetType.SETLE, Register.r10b()))
316317
val tmp = Label(getUUID())
317-
statements.add(MoveInstruction(Register.r10(), tmp))
318+
instructions.add(MoveInstruction(Register.r10(), tmp))
318319
tmp
319320
}
320321
BinOp.MORE_OR_EQ -> {
321-
statements.add(CmpInstruction(Register.r11(), Register.r10()))
322-
statements.add(SetInstruction(SetType.SETGE, Register.r10b()))
322+
instructions.add(CmpInstruction(Register.r11(), Register.r10()))
323+
instructions.add(SetInstruction(SetType.SETGE, Register.r10b()))
323324
val tmp = Label(getUUID())
324-
statements.add(MoveInstruction(Register.r10(), tmp))
325+
instructions.add(MoveInstruction(Register.r10(), tmp))
325326
tmp
326327
}
327328
BinOp.EQ -> {
328-
statements.add(CmpInstruction(Register.r11(), Register.r10()))
329-
statements.add(SetInstruction(SetType.SETE, Register.r10b()))
329+
instructions.add(CmpInstruction(Register.r11(), Register.r10()))
330+
instructions.add(SetInstruction(SetType.SETE, Register.r10b()))
330331
val tmp = Label(getUUID())
331-
statements.add(MoveInstruction(Register.r10(), tmp))
332+
instructions.add(MoveInstruction(Register.r10(), tmp))
332333
tmp
333334
}
334335
BinOp.NOT_EQ -> {
335-
statements.add(CmpInstruction(Register.r11(), Register.r10()))
336-
statements.add(SetInstruction(SetType.SETNE, Register.r10b()))
336+
instructions.add(CmpInstruction(Register.r11(), Register.r10()))
337+
instructions.add(SetInstruction(SetType.SETNE, Register.r10b()))
337338
val tmp = Label(getUUID())
338-
statements.add(MoveInstruction(Register.r10(), tmp))
339+
instructions.add(MoveInstruction(Register.r10(), tmp))
339340
tmp
340341
}
341342
BinOp.AND -> {
342-
statements.add(AndInstruction(Register.r10(), Register.r11()))
343+
instructions.add(AndInstruction(Register.r10(), Register.r11()))
343344
val tmp = Label(getUUID())
344-
statements.add(MoveInstruction(Register.r11(), tmp))
345+
instructions.add(MoveInstruction(Register.r11(), tmp))
345346
tmp
346347
}
347348
BinOp.OR -> {
348-
statements.add(OrInstruction(Register.r10(), Register.r11()))
349+
instructions.add(OrInstruction(Register.r10(), Register.r11()))
349350
val tmp = Label(getUUID())
350-
statements.add(MoveInstruction(Register.r11(), tmp))
351+
instructions.add(MoveInstruction(Register.r11(), tmp))
351352
tmp
352353
}
353354
}
@@ -356,17 +357,17 @@ fun irExprToLow(expr: IRExpr): List<Instruction> {
356357
val loc = traverse(expr.expr)
357358
when (expr.op) {
358359
UnaryOp.MINUS -> {
359-
statements.add(MoveInstruction(loc, Register.r10()))
360-
statements.add(NegInstruction(Register.r10()))
360+
instructions.add(MoveInstruction(loc, Register.r10()))
361+
instructions.add(NegInstruction(Register.r10()))
361362
val tmp = Label(getUUID())
362-
statements.add(MoveInstruction(Register.r10(), tmp))
363+
instructions.add(MoveInstruction(Register.r10(), tmp))
363364
tmp
364365
}
365366
UnaryOp.NOT -> {
366-
statements.add(MoveInstruction(loc, Register.r10()))
367-
statements.add(NotInstruction(Register.r10b()))
367+
instructions.add(MoveInstruction(loc, Register.r10()))
368+
instructions.add(NotInstruction(Register.r10b()))
368369
val tmp = Label(getUUID())
369-
statements.add(MoveInstruction(Register.r10(), tmp))
370+
instructions.add(MoveInstruction(Register.r10(), tmp))
370371
tmp
371372
}
372373
}
@@ -376,7 +377,7 @@ fun irExprToLow(expr: IRExpr): List<Instruction> {
376377
is IRIDLocation -> Label(location.name)
377378
is IRArrayLocation -> {
378379
val index = traverse(location.indexExpr)
379-
statements.add(MoveInstruction(index, Register.r10()))
380+
instructions.add(MoveInstruction(index, Register.r10()))
380381
ArrayAsm(location.name, Register.r10())
381382
}
382383
}
@@ -385,9 +386,72 @@ fun irExprToLow(expr: IRExpr): List<Instruction> {
385386
}
386387

387388
traverse(expr)
388-
return statements
389+
return instructions
389390
}
390391

391-
fun irStatementToLower(statements: IRStatement) {
392+
fun irStatementToLow(statement: IRStatement): List<Instruction> {
393+
val instructions = mutableListOf<Instruction>()
394+
395+
when (statement) {
396+
is IRDirectAssignStatement -> {
397+
val exprInstructions = irExprToLow(statement.expr)
398+
instructions.addAll(exprInstructions)
399+
val exprValLocation = (exprInstructions.last() as MoveInstruction).dest
400+
val rhs = when (val location = statement.location) {
401+
is IRIDLocation -> Label(location.name)
402+
is IRArrayLocation -> {
403+
val indexInstructions = irExprToLow(location.indexExpr)
404+
instructions.addAll(indexInstructions)
405+
val index = (indexInstructions.last() as MoveInstruction).dest
406+
instructions.add(MoveInstruction(index, Register.r10()))
407+
ArrayAsm(location.name, Register.r10())
408+
}
409+
}
410+
instructions.add(MoveInstruction(exprValLocation, Register.r10()))
411+
instructions.add(MoveInstruction(Register.r10(), rhs))
412+
}
413+
is IRIncrementStatement -> {
414+
val exprInstructions = irExprToLow(statement.expr)
415+
instructions.addAll(exprInstructions)
416+
val exprValLocation = (exprInstructions.last() as MoveInstruction).dest
417+
val rhs = when (val location = statement.location) {
418+
is IRIDLocation -> Label(location.name)
419+
is IRArrayLocation -> {
420+
val indexInstructions = irExprToLow(location.indexExpr)
421+
instructions.addAll(indexInstructions)
422+
val index = (indexInstructions.last() as MoveInstruction).dest
423+
instructions.add(MoveInstruction(index, Register.r10()))
424+
ArrayAsm(location.name, Register.r10())
425+
}
426+
}
427+
instructions.add(MoveInstruction(rhs, Register.r10()))
428+
instructions.add(AddInstruction(exprValLocation, Register.r10()))
429+
instructions.add(MoveInstruction(Register.r10(), rhs))
430+
}
431+
is IRDecrementStatement -> {
432+
val exprInstructions = irExprToLow(statement.expr)
433+
instructions.addAll(exprInstructions)
434+
val exprValLocation = (exprInstructions.last() as MoveInstruction).dest
435+
val rhs = when (val location = statement.location) {
436+
is IRIDLocation -> Label(location.name)
437+
is IRArrayLocation -> {
438+
val indexInstructions = irExprToLow(location.indexExpr)
439+
instructions.addAll(indexInstructions)
440+
val index = (indexInstructions.last() as MoveInstruction).dest
441+
instructions.add(MoveInstruction(index, Register.r10()))
442+
ArrayAsm(location.name, Register.r10())
443+
}
444+
}
445+
instructions.add(MoveInstruction(rhs, Register.r10()))
446+
instructions.add(SubInstruction(exprValLocation, Register.r10()))
447+
instructions.add(MoveInstruction(Register.r10(), rhs))
448+
}
449+
is IRInvokeStatement -> {
450+
val invokeInstructions = irExprToLow(statement.expr)
451+
instructions.addAll(invokeInstructions)
452+
}
453+
else -> throw IllegalStateException("shouldn't be calling for this statement: ${irToString(statement)}")
454+
}
392455

456+
return instructions
393457
}

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