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arm64: dts: rockchip: px30-ad-r35-mb: include rk618.dtsi
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> Change-Id: Ia96096216b2fad6ca86fcba7160aab9bcc8d9984
1 parent 8eca2cf commit 03aac86

5 files changed

Lines changed: 132 additions & 292 deletions

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‎arch/arm64/boot/dts/rockchip/px30-ad-r35-mb-rk618-dual-lvds.dts‎

Lines changed: 15 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,6 @@
44
*/
55

66
/dts-v1/;
7-
#include <dt-bindings/clock/rk618-cru.h>
87
#include "px30-ad-r35-mb.dtsi"
98

109
/ {
@@ -53,69 +52,27 @@
5352
auto-freq-en = <0>;
5453
};
5554

56-
&i2c0 {
55+
&rk618_lvds {
56+
dual-channel;
5757
status = "okay";
5858

59-
rk618@50 {
60-
compatible = "rockchip,rk618";
61-
reg = <0x50>;
62-
interrupt-parent = <&gpio2>;
63-
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
64-
pinctrl-names = "default";
65-
pinctrl-0 = <&i2s1_2ch_mclk>;
66-
clocks = <&cru SCLK_I2S1_OUT>;
67-
clock-names = "clkin";
68-
assigned-clocks = <&cru SCLK_I2S1_OUT>;
69-
assigned-clock-rates = <11289600>;
70-
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
71-
status = "okay";
72-
73-
clock: cru {
74-
compatible = "rockchip,rk618-cru";
75-
clocks = <&cru SCLK_I2S1_OUT>, <&cru DCLK_VOPL>;
76-
clock-names = "clkin", "lcdc0_dclkp";
77-
assigned-clocks = <&clock SCALER_PLLIN_CLK>,
78-
<&clock VIF_PLLIN_CLK>,
79-
<&clock SCALER_CLK>,
80-
<&clock VIF0_PRE_CLK>,
81-
<&clock CODEC_CLK>,
82-
<&clock DITHER_CLK>;
83-
assigned-clock-parents = <&cru SCLK_I2S1_OUT>,
84-
<&clock LCDC0_CLK>,
85-
<&clock SCALER_PLL_CLK>,
86-
<&clock VIF_PLL_CLK>,
87-
<&cru SCLK_I2S1_OUT>,
88-
<&clock VIF0_CLK>;
89-
#clock-cells = <1>;
90-
status = "okay";
91-
};
92-
93-
lvds {
94-
compatible = "rockchip,rk618-lvds";
95-
clocks = <&clock LVDS_CLK>;
96-
clock-names = "lvds";
97-
dual-channel;
98-
status = "okay";
99-
100-
ports {
101-
#address-cells = <1>;
102-
#size-cells = <0>;
59+
ports {
60+
#address-cells = <1>;
61+
#size-cells = <0>;
10362

104-
port@0 {
105-
reg = <0>;
63+
port@0 {
64+
reg = <0>;
10665

107-
lvds_in_rgb: endpoint {
108-
remote-endpoint = <&rgb_out_lvds>;
109-
};
110-
};
66+
lvds_in_rgb: endpoint {
67+
remote-endpoint = <&rgb_out_lvds>;
68+
};
69+
};
11170

112-
port@1 {
113-
reg = <1>;
71+
port@1 {
72+
reg = <1>;
11473

115-
lvds_out_panel: endpoint {
116-
remote-endpoint = <&panel_in_lvds>;
117-
};
118-
};
74+
lvds_out_panel: endpoint {
75+
remote-endpoint = <&panel_in_lvds>;
11976
};
12077
};
12178
};

‎arch/arm64/boot/dts/rockchip/px30-ad-r35-mb-rk618-hdmi-lvds.dts‎

Lines changed: 68 additions & 123 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,6 @@
55

66
/dts-v1/;
77
#include <dt-bindings/display/media-bus-format.h>
8-
#include <dt-bindings/clock/rk618-cru.h>
98
#include "px30-ad-r35-mb.dtsi"
109

1110
/ {
@@ -54,155 +53,101 @@
5453
auto-freq-en = <0>;
5554
};
5655

57-
&i2c0 {
56+
&rk618_hdmi {
5857
status = "okay";
5958

60-
rk618@50 {
61-
compatible = "rockchip,rk618";
62-
reg = <0x50>;
63-
interrupt-parent = <&gpio2>;
64-
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
65-
pinctrl-names = "default";
66-
pinctrl-0 = <&i2s1_2ch_mclk>;
67-
clocks = <&cru SCLK_I2S1_OUT>;
68-
clock-names = "clkin";
69-
assigned-clocks = <&cru SCLK_I2S1_OUT>;
70-
assigned-clock-rates = <11289600>;
71-
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
72-
status = "okay";
73-
74-
clock: cru {
75-
compatible = "rockchip,rk618-cru";
76-
clocks = <&cru SCLK_I2S1_OUT>, <&cru DCLK_VOPL>;
77-
clock-names = "clkin", "lcdc0_dclkp";
78-
assigned-clocks = <&clock SCALER_PLLIN_CLK>,
79-
<&clock VIF_PLLIN_CLK>,
80-
<&clock SCALER_CLK>,
81-
<&clock VIF0_PRE_CLK>,
82-
<&clock CODEC_CLK>,
83-
<&clock DITHER_CLK>;
84-
assigned-clock-parents = <&cru SCLK_I2S1_OUT>,
85-
<&clock LCDC0_CLK>,
86-
<&clock SCALER_PLL_CLK>,
87-
<&clock VIF_PLL_CLK>,
88-
<&cru SCLK_I2S1_OUT>,
89-
<&clock VIF0_CLK>;
90-
#clock-cells = <1>;
91-
status = "okay";
59+
ports {
60+
#address-cells = <1>;
61+
#size-cells = <0>;
62+
63+
port@0 {
64+
reg = <0>;
65+
66+
hdmi_in_vif: endpoint {
67+
remote-endpoint = <&vif_out_hdmi>;
68+
};
9269
};
9370

94-
hdmi {
95-
compatible = "rockchip,rk618-hdmi";
96-
clocks = <&clock HDMI_CLK>;
97-
clock-names = "hdmi";
98-
assigned-clocks = <&clock HDMI_CLK>;
99-
assigned-clock-parents = <&clock VIF0_CLK>;
100-
status = "okay";
101-
102-
ports {
103-
#address-cells = <1>;
104-
#size-cells = <0>;
105-
106-
port@0 {
107-
reg = <0>;
108-
109-
hdmi_in_vif: endpoint {
110-
remote-endpoint = <&vif_out_hdmi>;
111-
};
112-
};
113-
114-
port@1 {
115-
reg = <1>;
116-
117-
hdmi_out_scaler: endpoint {
118-
remote-endpoint = <&scaler_in_hdmi>;
119-
};
120-
};
71+
port@1 {
72+
reg = <1>;
73+
74+
hdmi_out_scaler: endpoint {
75+
remote-endpoint = <&scaler_in_hdmi>;
12176
};
12277
};
78+
};
79+
};
12380

124-
lvds {
125-
compatible = "rockchip,rk618-lvds";
126-
clocks = <&clock LVDS_CLK>;
127-
clock-names = "lvds";
128-
status = "okay";
81+
&rk618_lvds {
82+
status = "okay";
12983

130-
ports {
131-
#address-cells = <1>;
132-
#size-cells = <0>;
84+
ports {
85+
#address-cells = <1>;
86+
#size-cells = <0>;
13387

134-
port@0 {
135-
reg = <0>;
88+
port@0 {
89+
reg = <0>;
13690

137-
lvds_in_scaler: endpoint {
138-
remote-endpoint = <&scaler_out_lvds>;
139-
};
140-
};
91+
lvds_in_scaler: endpoint {
92+
remote-endpoint = <&scaler_out_lvds>;
93+
};
94+
};
14195

142-
port@1 {
143-
reg = <1>;
96+
port@1 {
97+
reg = <1>;
14498

145-
lvds_out_panel: endpoint {
146-
remote-endpoint = <&panel_in_lvds>;
147-
};
148-
};
99+
lvds_out_panel: endpoint {
100+
remote-endpoint = <&panel_in_lvds>;
149101
};
150102
};
103+
};
104+
};
151105

152-
scaler {
153-
compatible = "rockchip,rk618-scaler";
154-
clocks = <&clock SCALER_CLK>, <&clock VIF0_CLK>,
155-
<&clock DITHER_CLK>;
156-
clock-names = "scaler", "vif", "dither";
157-
status = "okay";
106+
&rk618_scaler {
107+
status = "okay";
158108

159-
ports {
160-
#address-cells = <1>;
161-
#size-cells = <0>;
109+
ports {
110+
#address-cells = <1>;
111+
#size-cells = <0>;
162112

163-
port@0 {
164-
reg = <0>;
113+
port@0 {
114+
reg = <0>;
165115

166-
scaler_in_hdmi: endpoint {
167-
remote-endpoint = <&hdmi_out_scaler>;
168-
};
169-
};
116+
scaler_in_hdmi: endpoint {
117+
remote-endpoint = <&hdmi_out_scaler>;
118+
};
119+
};
170120

171-
port@1 {
172-
reg = <1>;
121+
port@1 {
122+
reg = <1>;
173123

174-
scaler_out_lvds: endpoint {
175-
remote-endpoint = <&lvds_in_scaler>;
176-
};
177-
};
124+
scaler_out_lvds: endpoint {
125+
remote-endpoint = <&lvds_in_scaler>;
178126
};
179127
};
128+
};
129+
};
180130

181-
vif {
182-
compatible = "rockchip,rk618-vif";
183-
clocks = <&clock VIF0_CLK>, <&clock VIF0_PRE_CLK>;
184-
clock-names = "vif", "vif_pre";
185-
status = "okay";
131+
&rk618_vif {
132+
status = "okay";
186133

187-
ports {
188-
#address-cells = <1>;
189-
#size-cells = <0>;
134+
ports {
135+
#address-cells = <1>;
136+
#size-cells = <0>;
190137

191-
port@0 {
192-
reg = <0>;
138+
port@0 {
139+
reg = <0>;
193140

194-
vif_in_rgb: endpoint {
195-
remote-endpoint = <&rgb_out_vif>;
196-
};
197-
};
141+
vif_in_rgb: endpoint {
142+
remote-endpoint = <&rgb_out_vif>;
143+
};
144+
};
198145

199-
port@1 {
200-
reg = <1>;
146+
port@1 {
147+
reg = <1>;
201148

202-
vif_out_hdmi: endpoint {
203-
remote-endpoint = <&hdmi_in_vif>;
204-
};
205-
};
149+
vif_out_hdmi: endpoint {
150+
remote-endpoint = <&hdmi_in_vif>;
206151
};
207152
};
208153
};
@@ -237,5 +182,5 @@
237182

238183
&route_rgb {
239184
connect = <&vopl_out_rgb>;
240-
status = "okay";
185+
status = "disabled";
241186
};

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