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Merge remote-tracking branch 'v4.4/topic/coresight' into linux-linaro-lsk-v4.4
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‎Documentation/ABI/testing/sysfs-bus-coresight-devices-etb10‎

Lines changed: 62 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -6,13 +6,6 @@ Description: (RW) Add/remove a sink from a trace path. There can be multiple
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source for a single sink.
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ex: echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink
88

9-
What: /sys/bus/coresight/devices/<memory_map>.etb/status
10-
Date: November 2014
11-
KernelVersion: 3.19
12-
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
13-
Description: (R) List various control and status registers. The specific
14-
layout and content is driver specific.
15-
169
What: /sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr
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Date: November 2014
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KernelVersion: 3.19
@@ -22,3 +15,65 @@ Description: (RW) Disables write access to the Trace RAM by stopping the
2215
following the trigger event. The number of 32-bit words written
2316
into the Trace RAM following the trigger event is equal to the
2417
value stored in this register+1 (from ARM ETB-TRM).
18+
19+
What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rdp
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Date: March 2016
21+
KernelVersion: 4.7
22+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Defines the depth, in words, of the trace RAM in powers of
24+
2. The value is read directly from HW register RDP, 0x004.
25+
26+
What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/sts
27+
Date: March 2016
28+
KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the ETB status register. The value
31+
is read directly from HW register STS, 0x00C.
32+
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What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rrp
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the ETB RAM Read Pointer register
38+
that is used to read entries from the Trace RAM over the APB
39+
interface. The value is read directly from HW register RRP,
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0x014.
41+
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What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rwp
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the ETB RAM Write Pointer register
47+
that is used to sets the write pointer to write entries from
48+
the CoreSight bus into the Trace RAM. The value is read directly
49+
from HW register RWP, 0x018.
50+
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What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/trg
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Similar to "trigger_cntr" above except that this value is
56+
read directly from HW register TRG, 0x01C.
57+
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What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ctl
59+
Date: March 2016
60+
KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the ETB Control register. The value
63+
is read directly from HW register CTL, 0x020.
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What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffsr
66+
Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the ETB Formatter and Flush Status
70+
register. The value is read directly from HW register FFSR,
71+
0x300.
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What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffcr
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the ETB Formatter and Flush Control
78+
register. The value is read directly from HW register FFCR,
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0x304.

‎Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x‎

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Original file line numberDiff line numberDiff line change
@@ -359,6 +359,19 @@ Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Print the content of the Peripheral ID3 Register
360360
(0xFEC). The value is taken directly from the HW.
361361

362+
What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcconfig
363+
Date: February 2016
364+
KernelVersion: 4.07
365+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Print the content of the trace configuration register
367+
(0x010) as currently set by SW.
368+
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What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trctraceid
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Date: February 2016
371+
KernelVersion: 4.07
372+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Print the content of the trace ID register (0x040).
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362375
What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr0
363376
Date: April 2015
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KernelVersion: 4.01

‎Documentation/ABI/testing/sysfs-bus-coresight-devices-stm‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,53 @@
1+
What: /sys/bus/coresight/devices/<memory_map>.stm/enable_source
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Date: April 2016
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KernelVersion: 4.7
4+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
5+
Description: (RW) Enable/disable tracing on this specific trace macrocell.
6+
Enabling the trace macrocell implies it has been configured
7+
properly and a sink has been identified for it. The path
8+
of coresight components linking the source to the sink is
9+
configured and managed automatically by the coresight framework.
10+
11+
What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_enable
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Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
15+
Description: (RW) Provides access to the HW event enable register, used in
16+
conjunction with HW event bank select register.
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What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_select
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Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Gives access to the HW event block select register
23+
(STMHEBSR) in order to configure up to 256 channels. Used in
24+
conjunction with "hwevent_enable" register as described above.
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26+
What: /sys/bus/coresight/devices/<memory_map>.stm/port_enable
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Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Provides access to the stimulus port enable register
31+
(STMSPER). Used in conjunction with "port_select" described
32+
below.
33+
34+
What: /sys/bus/coresight/devices/<memory_map>.stm/port_select
35+
Date: April 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
38+
Description: (RW) Used to determine which bank of stimulus port bit in
39+
register STMSPER (see above) apply to.
40+
41+
What: /sys/bus/coresight/devices/<memory_map>.stm/status
42+
Date: April 2016
43+
KernelVersion: 4.7
44+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
45+
Description: (R) List various control and status registers. The specific
46+
layout and content is driver specific.
47+
48+
What: /sys/bus/coresight/devices/<memory_map>.stm/traceid
49+
Date: April 2016
50+
KernelVersion: 4.7
51+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
52+
Description: (RW) Holds the trace ID that will appear in the trace stream
53+
coming from this trace entity.

‎Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc‎

Lines changed: 77 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,3 +6,80 @@ Description: (RW) Disables write access to the Trace RAM by stopping the
66
formatter after a defined number of words have been stored
77
following the trigger event. Additional interface for this
88
driver are expected to be added as it matures.
9+
10+
What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rsz
11+
Date: March 2016
12+
KernelVersion: 4.7
13+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
14+
Description: (R) Defines the size, in 32-bit words, of the local RAM buffer.
15+
The value is read directly from HW register RSZ, 0x004.
16+
17+
What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/sts
18+
Date: March 2016
19+
KernelVersion: 4.7
20+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
21+
Description: (R) Shows the value held by the TMC status register. The value
22+
is read directly from HW register STS, 0x00C.
23+
24+
What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rrp
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Date: March 2016
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KernelVersion: 4.7
27+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
28+
Description: (R) Shows the value held by the TMC RAM Read Pointer register
29+
that is used to read entries from the Trace RAM over the APB
30+
interface. The value is read directly from HW register RRP,
31+
0x014.
32+
33+
What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rwp
34+
Date: March 2016
35+
KernelVersion: 4.7
36+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
37+
Description: (R) Shows the value held by the TMC RAM Write Pointer register
38+
that is used to sets the write pointer to write entries from
39+
the CoreSight bus into the Trace RAM. The value is read directly
40+
from HW register RWP, 0x018.
41+
42+
What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/trg
43+
Date: March 2016
44+
KernelVersion: 4.7
45+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
46+
Description: (R) Similar to "trigger_cntr" above except that this value is
47+
read directly from HW register TRG, 0x01C.
48+
49+
What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ctl
50+
Date: March 2016
51+
KernelVersion: 4.7
52+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
53+
Description: (R) Shows the value held by the TMC Control register. The value
54+
is read directly from HW register CTL, 0x020.
55+
56+
What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffsr
57+
Date: March 2016
58+
KernelVersion: 4.7
59+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
60+
Description: (R) Shows the value held by the TMC Formatter and Flush Status
61+
register. The value is read directly from HW register FFSR,
62+
0x300.
63+
64+
What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffcr
65+
Date: March 2016
66+
KernelVersion: 4.7
67+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
68+
Description: (R) Shows the value held by the TMC Formatter and Flush Control
69+
register. The value is read directly from HW register FFCR,
70+
0x304.
71+
72+
What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/mode
73+
Date: March 2016
74+
KernelVersion: 4.7
75+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
76+
Description: (R) Shows the value held by the TMC Mode register, which
77+
indicate the mode the device has been configured to enact. The
78+
The value is read directly from the MODE register, 0x028.
79+
80+
What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/devid
81+
Date: March 2016
82+
KernelVersion: 4.7
83+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
84+
Description: (R) Indicates the capabilities of the Coresight TMC.
85+
The value is read directly from the DEVID register, 0xFC8,

‎Documentation/ABI/testing/sysfs-class-stm‎

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Original file line numberDiff line numberDiff line change
@@ -12,3 +12,13 @@ KernelVersion: 4.3
1212
Contact: Alexander Shishkin <alexander.shishkin@linux.intel.com>
1313
Description:
1414
Shows the number of channels per master on this STM device.
15+
16+
What: /sys/class/stm/<stm>/hw_override
17+
Date: March 2016
18+
KernelVersion: 4.7
19+
Contact: Alexander Shishkin <alexander.shishkin@linux.intel.com>
20+
Description:
21+
Reads as 0 if master numbers in the STP stream produced by
22+
this stm device will match the master numbers assigned by
23+
the software or 1 if the stm hardware overrides software
24+
assigned masters.

‎Documentation/trace/coresight.txt‎

Lines changed: 35 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -190,8 +190,8 @@ expected to be accessed and controlled using those entries.
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Last but not least, "struct module *owner" is expected to be set to reflect
191191
the information carried in "THIS_MODULE".
192192

193-
How to use
194-
----------
193+
How to use the tracer modules
194+
-----------------------------
195195

196196
Before trace collection can start, a coresight sink needs to be identify.
197197
There is no limit on the amount of sinks (nor sources) that can be enabled at
@@ -297,3 +297,36 @@ Info Tracing enabled
297297
Instruction 13570831 0x8026B584 E28DD00C false ADD sp,sp,#0xc
298298
Instruction 0 0x8026B588 E8BD8000 true LDM sp!,{pc}
299299
Timestamp Timestamp: 17107041535
300+
301+
How to use the STM module
302+
-------------------------
303+
304+
Using the System Trace Macrocell module is the same as the tracers - the only
305+
difference is that clients are driving the trace capture rather
306+
than the program flow through the code.
307+
308+
As with any other CoreSight component, specifics about the STM tracer can be
309+
found in sysfs with more information on each entry being found in [1]:
310+
311+
root@genericarmv8:~# ls /sys/bus/coresight/devices/20100000.stm
312+
enable_source hwevent_select port_enable subsystem uevent
313+
hwevent_enable mgmt port_select traceid
314+
root@genericarmv8:~#
315+
316+
Like any other source a sink needs to be identified and the STM enabled before
317+
being used:
318+
319+
root@genericarmv8:~# echo 1 > /sys/bus/coresight/devices/20010000.etf/enable_sink
320+
root@genericarmv8:~# echo 1 > /sys/bus/coresight/devices/20100000.stm/enable_source
321+
322+
From there user space applications can request and use channels using the devfs
323+
interface provided for that purpose by the generic STM API:
324+
325+
root@genericarmv8:~# ls -l /dev/20100000.stm
326+
crw------- 1 root root 10, 61 Jan 3 18:11 /dev/20100000.stm
327+
root@genericarmv8:~#
328+
329+
Details on how to use the generic STM API can be found here [2].
330+
331+
[1]. Documentation/ABI/testing/sysfs-bus-coresight-devices-stm
332+
[2]. Documentation/trace/stm.txt

‎MAINTAINERS‎

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Original file line numberDiff line numberDiff line change
@@ -9356,6 +9356,7 @@ F: drivers/mmc/host/dw_mmc*
93569356
SYSTEM TRACE MODULE CLASS
93579357
M: Alexander Shishkin <alexander.shishkin@linux.intel.com>
93589358
S: Maintained
9359+
T: git git://git.kernel.org/pub/scm/linux/kernel/git/ash/stm.git
93599360
F: Documentation/trace/stm.txt
93609361
F: drivers/hwtracing/stm/
93619362
F: include/linux/stm.h

‎drivers/hwtracing/coresight/Kconfig‎

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,11 +4,12 @@
44
menuconfig CORESIGHT
55
bool "CoreSight Tracing Support"
66
select ARM_AMBA
7+
select PERF_EVENTS
78
help
89
This framework provides a kernel interface for the CoreSight debug
910
and trace drivers to register themselves with. It's intended to build
1011
a topological view of the CoreSight components based on a DT
11-
specification and configure the right serie of components when a
12+
specification and configure the right series of components when a
1213
trace source gets enabled.
1314

1415
if CORESIGHT
@@ -77,4 +78,15 @@ config CORESIGHT_QCOM_REPLICATOR
7778
programmable ATB replicator sends the ATB trace stream from the
7879
ETB/ETF to the TPIUi and ETR.
7980

81+
config CORESIGHT_STM
82+
bool "CoreSight System Trace Macrocell driver"
83+
depends on (ARM && !(CPU_32v3 || CPU_32v4 || CPU_32v4T)) || ARM64
84+
select CORESIGHT_LINKS_AND_SINKS
85+
select STM
86+
help
87+
This driver provides support for hardware assisted software
88+
instrumentation based tracing. This is primarily used for
89+
logging useful software events or data coming from various entities
90+
in the system, possibly running different OSs
91+
8092
endif

‎drivers/hwtracing/coresight/Makefile‎

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,18 @@
11
#
22
# Makefile for CoreSight drivers.
33
#
4-
obj-$(CONFIG_CORESIGHT) += coresight.o
4+
obj-$(CONFIG_CORESIGHT) += coresight.o coresight-etm-perf.o
55
obj-$(CONFIG_OF) += of_coresight.o
6-
obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
6+
obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o \
7+
coresight-tmc-etf.o \
8+
coresight-tmc-etr.o
79
obj-$(CONFIG_CORESIGHT_SINK_TPIU) += coresight-tpiu.o
810
obj-$(CONFIG_CORESIGHT_SINK_ETBV10) += coresight-etb10.o
911
obj-$(CONFIG_CORESIGHT_LINKS_AND_SINKS) += coresight-funnel.o \
1012
coresight-replicator.o
11-
obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o coresight-etm-cp14.o
12-
obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o
13+
obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o coresight-etm-cp14.o \
14+
coresight-etm3x-sysfs.o
15+
obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o \
16+
coresight-etm4x-sysfs.o
1317
obj-$(CONFIG_CORESIGHT_QCOM_REPLICATOR) += coresight-replicator-qcom.o
18+
obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o

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