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arm64: dts: rockchip: rk3368-evb-ext-rk618: include rk618.dtsi
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> Change-Id: I7c84ddb05d0f95d0205edce87cfaccb35a32f667
1 parent f44baa5 commit 80bbf43

1 file changed

Lines changed: 121 additions & 155 deletions

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‎arch/arm64/boot/dts/rockchip/rk3368-evb-ext-rk618-avb.dts‎

Lines changed: 121 additions & 155 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,6 @@
44
*/
55

66
/dts-v1/;
7-
#include <dt-bindings/clock/rk618-cru.h>
87
#include "rk3368-808.dtsi"
98

109
/ {
@@ -41,186 +40,154 @@
4140
&i2c2 {
4241
status = "okay";
4342

44-
rk618@50 {
45-
compatible = "rockchip,rk618";
43+
rk618: rk618@50 {
4644
reg = <0x50>;
4745
interrupt-parent = <&gpio1>;
4846
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
4947
pinctrl-names = "default";
5048
pinctrl-0 = <&i2s_8ch_mclk>;
51-
clocks = <&cru SCLK_I2S_8CH_OUT>;
52-
clock-names = "clkin";
5349
assigned-clocks = <&cru SCLK_I2S_8CH_OUT>;
5450
assigned-clock-rates = <11289600>;
5551
reset-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>;
5652
status = "okay";
53+
};
54+
};
55+
56+
#include <arm/rk618.dtsi>
57+
58+
&rk618_clkin {
59+
clocks = <&cru SCLK_I2S_8CH_OUT>;
60+
};
61+
62+
&rk618_lcdc0_dclkp {
63+
clocks = <&cru DCLK_VOP>;
64+
};
65+
66+
&rk618_dsi {
67+
status = "okay";
68+
69+
panel@0 {
70+
compatible = "simple-panel-dsi";
71+
reg = <0>;
72+
backlight = <&backlight>;
73+
power-supply = <&vcc_lcd>;
74+
prepare-delay-ms = <120>;
75+
enable-delay-ms = <120>;
76+
disable-delay-ms = <120>;
77+
unprepare-delay-ms = <120>;
78+
79+
dsi,flags = <(MIPI_DSI_MODE_VIDEO |
80+
MIPI_DSI_MODE_VIDEO_BURST |
81+
MIPI_DSI_MODE_LPM |
82+
MIPI_DSI_MODE_EOT_PACKET)>;
83+
dsi,format = <MIPI_DSI_FMT_RGB888>;
84+
dsi,lanes = <4>;
85+
86+
display-timings {
87+
native-mode = <&timing>;
88+
89+
timing: timing {
90+
clock-frequency = <160000000>;
91+
hactive = <1200>;
92+
vactive = <1920>;
93+
hback-porch = <60>;
94+
hfront-porch = <80>;
95+
vback-porch = <25>;
96+
vfront-porch = <35>;
97+
hsync-len = <1>;
98+
vsync-len = <1>;
99+
hsync-active = <0>;
100+
vsync-active = <0>;
101+
de-active = <0>;
102+
pixelclk-active = <0>;
103+
};
104+
};
105+
};
106+
107+
ports {
108+
#address-cells = <1>;
109+
#size-cells = <0>;
57110

58-
rk618_cru: cru {
59-
compatible = "rockchip,rk618-cru";
60-
clocks = <&cru SCLK_I2S_8CH_OUT>, <&cru DCLK_VOP>;
61-
clock-names = "clkin", "lcdc0_dclkp";
62-
assigned-clocks = <&rk618_cru SCALER_PLLIN_CLK>,
63-
<&rk618_cru VIF_PLLIN_CLK>,
64-
<&rk618_cru SCALER_CLK>,
65-
<&rk618_cru VIF0_PRE_CLK>,
66-
<&rk618_cru CODEC_CLK>,
67-
<&rk618_cru DITHER_CLK>;
68-
assigned-clock-parents = <&cru SCLK_I2S_8CH_OUT>,
69-
<&rk618_cru LCDC0_CLK>,
70-
<&rk618_cru SCALER_PLL_CLK>,
71-
<&rk618_cru VIF_PLL_CLK>,
72-
<&cru SCLK_I2S_8CH_OUT>,
73-
<&rk618_cru VIF0_CLK>;
74-
#clock-cells = <1>;
75-
status = "okay";
111+
port@0 {
112+
reg = <0>;
113+
114+
dsi_in_scaler: endpoint {
115+
remote-endpoint = <&scaler_out_dsi>;
116+
};
76117
};
118+
};
119+
};
120+
121+
&rk618_vif {
122+
status = "okay";
123+
124+
ports {
125+
#address-cells = <1>;
126+
#size-cells = <0>;
127+
128+
port@0 {
129+
reg = <0>;
77130

78-
hdmi {
79-
compatible = "rockchip,rk618-hdmi";
80-
clocks = <&rk618_cru HDMI_CLK>;
81-
clock-names = "hdmi";
82-
assigned-clocks = <&rk618_cru HDMI_CLK>;
83-
assigned-clock-parents = <&rk618_cru VIF0_CLK>;
84-
status = "okay";
85-
86-
ports {
87-
#address-cells = <1>;
88-
#size-cells = <0>;
89-
90-
port@0 {
91-
reg = <0>;
92-
93-
hdmi_in_vif: endpoint {
94-
remote-endpoint = <&vif_out_hdmi>;
95-
};
96-
};
97-
98-
port@1 {
99-
reg = <1>;
100-
101-
hdmi_out_scaler: endpoint {
102-
remote-endpoint = <&scaler_in_hdmi>;
103-
};
104-
};
131+
vif_in_rgb: endpoint {
132+
remote-endpoint = <&rgb_out_vif>;
105133
};
106134
};
107135

108-
scaler {
109-
compatible = "rockchip,rk618-scaler";
110-
clocks = <&rk618_cru SCALER_CLK>,
111-
<&rk618_cru VIF0_CLK>,
112-
<&rk618_cru DITHER_CLK>;
113-
clock-names = "scaler", "vif", "dither";
114-
status = "okay";
115-
116-
ports {
117-
#address-cells = <1>;
118-
#size-cells = <0>;
119-
120-
port@0 {
121-
reg = <0>;
122-
123-
scaler_in_hdmi: endpoint {
124-
remote-endpoint = <&hdmi_out_scaler>;
125-
};
126-
};
127-
128-
port@1 {
129-
reg = <1>;
130-
131-
scaler_out_dsi: endpoint {
132-
remote-endpoint = <&dsi_in_scaler>;
133-
};
134-
};
136+
port@1 {
137+
reg = <1>;
138+
139+
vif_out_hdmi: endpoint {
140+
remote-endpoint = <&hdmi_in_vif>;
135141
};
136142
};
143+
};
144+
};
137145

138-
vif {
139-
compatible = "rockchip,rk618-vif";
140-
clocks = <&rk618_cru VIF0_CLK>,
141-
<&rk618_cru VIF0_PRE_CLK>;
142-
clock-names = "vif", "vif_pre";
143-
status = "okay";
146+
&rk618_hdmi {
147+
status = "okay";
144148

145-
ports {
146-
#address-cells = <1>;
147-
#size-cells = <0>;
149+
ports {
150+
#address-cells = <1>;
151+
#size-cells = <0>;
148152

149-
port@0 {
150-
reg = <0>;
153+
port@0 {
154+
reg = <0>;
151155

152-
vif_in_rgb: endpoint {
153-
remote-endpoint = <&rgb_out_vif>;
154-
};
155-
};
156+
hdmi_in_vif: endpoint {
157+
remote-endpoint = <&vif_out_hdmi>;
158+
};
159+
};
156160

157-
port@1 {
158-
reg = <1>;
161+
port@1 {
162+
reg = <1>;
159163

160-
vif_out_hdmi: endpoint {
161-
remote-endpoint = <&hdmi_in_vif>;
162-
};
163-
};
164+
hdmi_out_scaler: endpoint {
165+
remote-endpoint = <&scaler_in_hdmi>;
164166
};
165167
};
168+
};
169+
};
170+
171+
&rk618_scaler {
172+
status = "okay";
173+
174+
ports {
175+
#address-cells = <1>;
176+
#size-cells = <0>;
177+
178+
port@0 {
179+
reg = <0>;
166180

167-
dsi {
168-
compatible = "rockchip,rk618-dsi";
169-
clocks = <&rk618_cru MIPI_CLK>;
170-
clock-names = "dsi";
171-
#address-cells = <1>;
172-
#size-cells = <0>;
173-
status = "okay";
174-
175-
ports {
176-
#address-cells = <1>;
177-
#size-cells = <0>;
178-
179-
port@0 {
180-
reg = <0>;
181-
182-
dsi_in_scaler: endpoint {
183-
remote-endpoint = <&scaler_out_dsi>;
184-
};
185-
};
181+
scaler_in_hdmi: endpoint {
182+
remote-endpoint = <&hdmi_out_scaler>;
186183
};
184+
};
185+
186+
port@1 {
187+
reg = <1>;
187188

188-
panel@0 {
189-
compatible = "simple-panel-dsi";
190-
reg = <0>;
191-
backlight = <&backlight>;
192-
power-supply = <&vcc_lcd>;
193-
prepare-delay-ms = <120>;
194-
enable-delay-ms = <120>;
195-
disable-delay-ms = <120>;
196-
unprepare-delay-ms = <120>;
197-
198-
dsi,flags = <(MIPI_DSI_MODE_VIDEO |
199-
MIPI_DSI_MODE_VIDEO_BURST |
200-
MIPI_DSI_MODE_LPM |
201-
MIPI_DSI_MODE_EOT_PACKET)>;
202-
dsi,format = <MIPI_DSI_FMT_RGB888>;
203-
dsi,lanes = <4>;
204-
205-
display-timings {
206-
native-mode = <&timing>;
207-
208-
timing: timing {
209-
clock-frequency = <160000000>;
210-
hactive = <1200>;
211-
vactive = <1920>;
212-
hback-porch = <60>;
213-
hfront-porch = <80>;
214-
vback-porch = <25>;
215-
vfront-porch = <35>;
216-
hsync-len = <1>;
217-
vsync-len = <1>;
218-
hsync-active = <0>;
219-
vsync-active = <0>;
220-
de-active = <0>;
221-
pixelclk-active = <0>;
222-
};
223-
};
189+
scaler_out_dsi: endpoint {
190+
remote-endpoint = <&dsi_in_scaler>;
224191
};
225192
};
226193
};
@@ -265,6 +232,5 @@
265232
};
266233

267234
&route_rgb {
268-
/delete-property/ logo,uboot;
269-
status = "okay";
235+
status = "disabled";
270236
};

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