MINIARM: clk: rockchip: add some clock settings

Change-Id: I5f172106258f9dcb5617b245f729b661feacc92c
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>

Author: yueshu

drivers/clk/rockchip/clk-rk3288.c

@@ -100,6 +100,29 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
 	RK3066_PLL_RATE( 216000000, 1, 72, 8),
 	RK3066_PLL_RATE( 148500000, 2, 99, 8),
 	RK3066_PLL_RATE( 126000000, 1, 84, 16),
+	RK3066_PLL_RATE_NB( 241500000, 2, 161, 8, 1),
+	RK3066_PLL_RATE( 252000000, 1, 84, 8),
+	RK3066_PLL_RATE( 216000000, 1, 72, 8),
+	RK3066_PLL_RATE( 148500000, 8, 693, 14),
+	RK3066_PLL_RATE( 135000000, 4, 315, 14),
+	RK3066_PLL_RATE( 126000000, 1, 84, 16),
+	RK3066_PLL_RATE( 119000000, 3, 238, 16),
+	RK3066_PLL_RATE( 108000000, 1, 72, 16),
+	RK3066_PLL_RATE( 88750000, 6, 355, 16),
+	RK3066_PLL_RATE( 71000000, 3, 142, 16),
+	RK3066_PLL_RATE( 74250000, 8, 297, 12),
+	RK3066_PLL_RATE( 78750000, 4, 210, 16),
+	RK3066_PLL_RATE( 78800000, 15, 788, 16),
+	RK3066_PLL_RATE( 75000000, 2, 100, 16),
+	RK3066_PLL_RATE( 65000000, 3, 130, 16),
+	RK3066_PLL_RATE( 136750000, 8, 547, 12),
+	RK3066_PLL_RATE( 106500000, 1, 71, 16),
+	RK3066_PLL_RATE( 88750000, 6, 355, 16),
+	RK3066_PLL_RATE( 67500000, 8, 315, 14),
+	RK3066_PLL_RATE( 49500000, 1, 33, 16),
+	RK3066_PLL_RATE( 40000000, 3, 80, 16),
+	RK3066_PLL_RATE( 36000000, 1, 24, 16),
+	RK3066_PLL_RATE( 35500000, 3, 71, 16),
 	RK3066_PLL_RATE(  48000000, 1, 64, 32),
 	{ /* sentinel */ },
 };