arm64: dts: rockchip: rk1808 fix clk_32k_ioe setting

This patch will move clk_32k_ioe setting from core dtsi to rk1808 evb
which has pmic with 32k clock and connect to RK1808 SoC.

Fix 'commit 5684cdd("arm64: dts: rockchip: rk1808: assigned-clock-parents for clk_32k_ioe")'
Fix 'commit b1680c7("arm64: dts: rockchip: rk1808: add pinctrl for clkin/out_32k")'

For board with 32k clock out from pmic and put to RK1808, like evb-v10,
the clk32k_ioe/gpio0_c2 pin (aw13) should be pull normal.

For board with clk32k_ioe/gpio0_c2 float, the aw13 should be pull down.

Change-Id: I4961ecb8802c6cfbe2af4af0cca955cf920f65da
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

Author: jayxurockchip

arch/arm64/boot/dts/rockchip/rk1808-evb-x4.dts

@@ -46,15 +46,12 @@
 
 &cru {
 	assigned-clocks =
-		<&cru SCLK_32K_IOE>,
 		<&cru PLL_GPLL>, <&cru PLL_CPLL>,
 		<&cru PLL_PPLL>, <&cru ARMCLK>,
 		<&cru MSCLK_PERI>, <&cru LSCLK_PERI>,
 		<&cru HSCLK_BUS_PRE>, <&cru MSCLK_BUS_PRE>,
 		<&cru LSCLK_BUS_PRE>, <&cru DCLK_VOPRAW>;
-	assigned-clock-parents = <&xin32k>;
 	assigned-clock-rates =
-		<32768>,
 		<1188000000>, <1000000000>,
 		<100000000>, <816000000>,
 		<200000000>, <100000000>,

arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi

@@ -208,8 +208,17 @@
 	wireless_wlan: wireless-wlan {
 		compatible = "wlan-platdata";
 		rockchip,grf = <&grf>;
+		/*
+		 * Note:
+		 * Set clk_32k_ioe iomux, clock rate and parent, finally
+		 * intent to set pull normal for clk32k_io/gpio0_c2(aw13)
+		 * A normal state is better for 32k clock signal quality.
+		 */
 		pinctrl-names = "default";
-		pinctrl-0 = <&wifi_wake_host>;
+		pinctrl-0 = <&wifi_wake_host &clkin_32k>;
+		assigned-clocks = <&cru SCLK_32K_IOE>;
+		assigned-clock-rates = <32768>;
+		assigned-clock-parents = <&xin32k>;
 		wifi_chip_type = "ap6212";
 		WIFI,host_wake_irq = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>;
 		status = "okay";

arch/arm64/boot/dts/rockchip/rk1808.dtsi

@@ -293,8 +293,6 @@
 		clock-frequency = <32768>;
 		clock-output-names = "xin32k";
 		#clock-cells = <0>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&clkin_32k>;
 	};
 
 	pcie0: pcie@fc400000 {
@@ -645,15 +643,12 @@
 		#reset-cells = <1>;
 
 		assigned-clocks =
-			<&cru SCLK_32K_IOE>,
 			<&cru PLL_GPLL>, <&cru PLL_CPLL>,
 			<&cru PLL_PPLL>, <&cru ARMCLK>,
 			<&cru MSCLK_PERI>, <&cru LSCLK_PERI>,
 			<&cru HSCLK_BUS_PRE>, <&cru MSCLK_BUS_PRE>,
 			<&cru LSCLK_BUS_PRE>;
-		assigned-clock-parents = <&xin32k>;
 		assigned-clock-rates =
-			<32768>,
 			<1188000000>, <1000000000>,
 			<100000000>, <816000000>,
 			<200000000>, <100000000>,