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wasm2c: fix SIMD_FORCE_READ constraint for V-incapable RISC-V targets #2880

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Merged
shravanrn merged 1 commit into from
Oct 20, 2026
Merged

wasm2c: fix SIMD_FORCE_READ constraint for V-incapable RISC-V targets #2880

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2 changes: 1 addition & 1 deletion src/prebuilt/wasm2c_simd_source_declarations.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ R"w2c_template(#elif defined(__aarch64__)
)w2c_template"
R"w2c_template(#define SIMD_FORCE_READ(var) __asm__("" ::"w"(var));
)w2c_template"
R"w2c_template(#elif defined(__riscv)
R"w2c_template(#elif defined(__riscv) && defined(__riscv_vector)
)w2c_template"
R"w2c_template(#define SIMD_FORCE_READ(var) __asm__("" ::"vr"(var));
)w2c_template"
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2 changes: 1 addition & 1 deletion src/template/wasm2c_simd.declarations.c
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@
#define SIMD_FORCE_READ(var) __asm__("" ::"x"(var));
#elif defined(__aarch64__)
#define SIMD_FORCE_READ(var) __asm__("" ::"w"(var));
#elif defined(__riscv)
#elif defined(__riscv) && defined(__riscv_vector)

@shravanrn shravanrn Oct 19, 2026

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This looks fine. Could you send a PR with only the RISC-v change that is not stacked on the PowerPC and default case change so we can land this separately?

@CSharperMantle CSharperMantle Oct 20, 2026

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Okay. See also #2878 (comment).

#define SIMD_FORCE_READ(var) __asm__("" ::"vr"(var));
#elif defined(__s390x__)
#define SIMD_FORCE_READ(var) __asm__("" ::"d"(var));
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