alif/ospi_flash: Fix XIP for 8-bit instructions (ISSI).

Disable XIP instruction DDR for 8-bit instructions.

Signed-off-by: iabdalkader <i.abdalkader@gmail.com>

Author: iabdalkader

ports/alif/ospi_ext.c

@@ -28,8 +28,6 @@
 #include "ospi_ext.h"
 #include "ospi_xip_user.h"
 
-#define INST_L16bit (3)
-
 static void ospi_xip_disable(ospi_flash_cfg_t *ospi_cfg) {
     ospi_cfg->aes_regs->aes_control &= ~AES_CONTROL_XIP_EN;
 }
@@ -208,7 +206,7 @@ void ospi_setup_write_ext(ospi_flash_cfg_t *ospi_cfg, bool rxds, uint32_t inst_l
     spi_enable(ospi_cfg);
 }
 
-void ospi_xip_enter_16bit_cmd(ospi_flash_cfg_t *ospi_cfg, uint32_t data_len, uint16_t incr_command, uint16_t wrap_command, uint16_t read_dummy_cycles) {
+void ospi_xip_enter_ext(ospi_flash_cfg_t *ospi_cfg, uint32_t inst_len, uint32_t data_len, uint16_t incr_command, uint16_t wrap_command, uint16_t read_dummy_cycles) {
     spi_disable(ospi_cfg);
 
     uint32_t val = CTRLR0_IS_MST
@@ -224,12 +222,11 @@ void ospi_xip_enter_16bit_cmd(ospi_flash_cfg_t *ospi_cfg, uint32_t data_len, uin
     val = (OCTAL << XIP_CTRL_FRF_OFFSET)
         | (0x2 << XIP_CTRL_TRANS_TYPE_OFFSET)
         | (ADDR_L32bit << XIP_CTRL_ADDR_L_OFFSET)
-        | (INST_L16bit << XIP_CTRL_INST_L_OFFSET)
+        | (inst_len << XIP_CTRL_INST_L_OFFSET)
         | (0x0 << XIP_CTRL_MD_BITS_EN_OFFSET)
         | (read_dummy_cycles << XIP_CTRL_WAIT_CYCLES_OFFSET)
         | (0x1 << XIP_CTRL_DFC_HC_OFFSET)
         | (ospi_cfg->ddr_en << XIP_CTRL_DDR_EN_OFFSET)
-        | (ospi_cfg->ddr_en << XIP_CTRL_INST_DDR_EN_OFFSET)
         | (0x1 << XIP_CTRL_RXDS_EN_OFFSET)
         | (0x1 << XIP_CTRL_INST_EN_OFFSET)
         | (0x0 << XIP_CTRL_CONT_XFER_EN_OFFSET)
@@ -239,6 +236,10 @@ void ospi_xip_enter_16bit_cmd(ospi_flash_cfg_t *ospi_cfg, uint32_t data_len, uin
         | (0x0 << XIP_PREFETCH_EN_OFFSET)
         | (0x0 << XIP_CTRL_RXDS_VL_EN_OFFSET);
 
+    if (inst_len == OSPI_INST_L_16bit) {
+        val |= 1 << XIP_CTRL_INST_DDR_EN_OFFSET;
+    }
+
     ospi_writel(ospi_cfg, xip_ctrl, val);
 
     ospi_writel(ospi_cfg, rx_sample_dly, 4);
@@ -254,7 +255,7 @@ void ospi_xip_enter_16bit_cmd(ospi_flash_cfg_t *ospi_cfg, uint32_t data_len, uin
     ospi_xip_enable(ospi_cfg);
 }
 
-void ospi_xip_exit_16bit_cmd(ospi_flash_cfg_t *ospi_cfg, uint16_t incr_command, uint16_t wrap_command) {
+void ospi_xip_exit_ext(ospi_flash_cfg_t *ospi_cfg, uint32_t inst_len, uint16_t incr_command, uint16_t wrap_command) {
     spi_disable(ospi_cfg);
 
     uint32_t val = CTRLR0_IS_MST
@@ -272,7 +273,7 @@ void ospi_xip_exit_16bit_cmd(ospi_flash_cfg_t *ospi_cfg, uint16_t incr_command,
         | (2 << CTRLR0_XIP_MBL_OFFSET)
         | (1 << CTRLR0_XIP_DFS_HC_OFFSET)
         | (1 << CTRLR0_XIP_INST_EN_OFFSET)
-        | (CTRLR0_INST_L_16bit << CTRLR0_INST_L_OFFSET)
+        | (inst_len << CTRLR0_INST_L_OFFSET)
         | (ospi_cfg->addrlen) << (CTRLR0_ADDR_L_OFFSET)
         | (ospi_cfg->wait_cycles << CTRLR0_WAIT_CYCLES_OFFSET);
 

ports/alif/ospi_ext.h

@@ -51,7 +51,7 @@ int ospi_recv_blocking_32bit_data(ospi_flash_cfg_t *ospi_cfg, uint32_t command,
 
 void ospi_setup_write_ext(ospi_flash_cfg_t *ospi_cfg, bool rxds, uint32_t inst_len, uint32_t addr_len, uint32_t data_len);
 
-void ospi_xip_enter_16bit_cmd(ospi_flash_cfg_t *ospi_cfg, uint32_t data_len, uint16_t incr_command, uint16_t wrap_command, uint16_t read_dummy_cycles);
-void ospi_xip_exit_16bit_cmd(ospi_flash_cfg_t *ospi_cfg, uint16_t incr_command, uint16_t wrap_command);
+void ospi_xip_enter_ext(ospi_flash_cfg_t *ospi_cfg, uint32_t inst_len, uint32_t data_len, uint16_t incr_command, uint16_t wrap_command, uint16_t read_dummy_cycles);
+void ospi_xip_exit_ext(ospi_flash_cfg_t *ospi_cfg, uint32_t inst_len, uint16_t incr_command, uint16_t wrap_command);
 
 #endif // MICROPY_INCLUDED_ALIF_OSPI_EXT_H

ports/alif/ospi_flash.c

@@ -318,7 +318,8 @@ static int ospi_flash_xip_enter(ospi_flash_t *self) {
     if (!self->xip_active) {
         uint32_t irq_state = disable_irq();
         self->xip_active = true;
-        ospi_xip_enter_16bit_cmd(&self->cfg, self->set->xip_data_len, self->set->read_command, self->set->read_command, self->set->read_dummy_cycles);
+        ospi_xip_enter_ext(&self->cfg, self->set->inst_len, self->set->xip_data_len,
+            self->set->read_command, self->set->read_command, self->set->read_dummy_cycles);
         enable_irq(irq_state);
     }
     return 0;
@@ -327,7 +328,7 @@ static int ospi_flash_xip_enter(ospi_flash_t *self) {
 static int ospi_flash_xip_exit(ospi_flash_t *self) {
     if (self->xip_active) {
         uint32_t irq_state = disable_irq();
-        ospi_xip_exit_16bit_cmd(&self->cfg, self->set->read_command, self->set->read_command);
+        ospi_xip_exit_ext(&self->cfg, self->set->inst_len, self->set->read_command, self->set->read_command);
         self->xip_active = false;
         enable_irq(irq_state);
     }