😉
Preparing
pursuing M.Tech @ EE6, IITB
Mechatronics Engineer
- IIT Bombay
-
22:06
(UTC +05:30) - https://harivikinesh.github.io/portfolio/
- in/hari-vikinesh
- _hari_vikinesh_
Highlights
- Pro
Pinned Loading
-
MTech-EE-25-28/riscv_soc_hw
MTech-EE-25-28/riscv_soc_hw PublicEE 705 - VLSI Design Lab, Course Project (RISC-V Soc + Hardware Accelerator)
Verilog 6
-
-
-
-
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.


