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jonasjelonekAndi Shyti
jonasjelonek
authored and
Andi Shyti
committed
i2c: rtl9300: use regmap fields and API for registers
Adapt the RTL9300 I2C controller driver to use more of the regmap API, especially make use of reg_field and regmap_field instead of macros to represent registers. Most register operations are performed through regmap_field_* API then. Handle SCL selection using separate chip-specific functions since this is already known to differ between the Realtek SoC families in such a way that this cannot be properly handled using just a different reg_field. This makes it easier to add support for newer generations or to handle differences between specific revisions within a series. Just by defining a separate driver data structure with the corresponding register field definitions and linking it to a new compatible. Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com> Tested-by: Sven Eckelmann <sven@narfation.org> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz> # On RTL9302C based board Tested-by: Markus Stockhausen <markus.stockhausen@gmx.de> Signed-off-by: Andi Shyti <andi.shyti@kernel.org> Link: https://lore.kernel.org/r/20250927101931.71575-2-jelonek.jonas@gmail.com
1 parent d3c2191 commit 85f1c01

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Lines changed: 124 additions & 68 deletions

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‎drivers/i2c/busses/i2c-rtl9300.c‎

Lines changed: 124 additions & 68 deletions
Original file line numberDiff line numberDiff line change
@@ -23,97 +23,117 @@ struct rtl9300_i2c_chan {
2323
u8 sda_pin;
2424
};
2525

26+
enum rtl9300_i2c_reg_scope {
27+
REG_SCOPE_GLOBAL,
28+
REG_SCOPE_MASTER,
29+
};
30+
31+
struct rtl9300_i2c_reg_field {
32+
struct reg_field field;
33+
enum rtl9300_i2c_reg_scope scope;
34+
};
35+
36+
enum rtl9300_i2c_reg_fields {
37+
F_DATA_WIDTH = 0,
38+
F_DEV_ADDR,
39+
F_I2C_FAIL,
40+
F_I2C_TRIG,
41+
F_MEM_ADDR,
42+
F_MEM_ADDR_WIDTH,
43+
F_RD_MODE,
44+
F_RWOP,
45+
F_SCL_FREQ,
46+
F_SCL_SEL,
47+
F_SDA_OUT_SEL,
48+
F_SDA_SEL,
49+
50+
/* keep last */
51+
F_NUM_FIELDS
52+
};
53+
54+
struct rtl9300_i2c_drv_data {
55+
struct rtl9300_i2c_reg_field field_desc[F_NUM_FIELDS];
56+
int (*select_scl)(struct rtl9300_i2c *i2c, u8 scl);
57+
u32 data_reg;
58+
u8 max_nchan;
59+
};
60+
2661
#define RTL9300_I2C_MUX_NCHAN 8
2762

2863
struct rtl9300_i2c {
2964
struct regmap *regmap;
3065
struct device *dev;
3166
struct rtl9300_i2c_chan chans[RTL9300_I2C_MUX_NCHAN];
67+
struct regmap_field *fields[F_NUM_FIELDS];
3268
u32 reg_base;
69+
u32 data_reg;
3370
u8 sda_pin;
3471
struct mutex lock;
3572
};
3673

3774
#define RTL9300_I2C_MST_CTRL1 0x0
38-
#define RTL9300_I2C_MST_CTRL1_MEM_ADDR_OFS 8
39-
#define RTL9300_I2C_MST_CTRL1_MEM_ADDR_MASK GENMASK(31, 8)
40-
#define RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_OFS 4
41-
#define RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_MASK GENMASK(6, 4)
42-
#define RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL BIT(3)
43-
#define RTL9300_I2C_MST_CTRL1_RWOP BIT(2)
44-
#define RTL9300_I2C_MST_CTRL1_I2C_FAIL BIT(1)
45-
#define RTL9300_I2C_MST_CTRL1_I2C_TRIG BIT(0)
4675
#define RTL9300_I2C_MST_CTRL2 0x4
47-
#define RTL9300_I2C_MST_CTRL2_RD_MODE BIT(15)
48-
#define RTL9300_I2C_MST_CTRL2_DEV_ADDR_OFS 8
49-
#define RTL9300_I2C_MST_CTRL2_DEV_ADDR_MASK GENMASK(14, 8)
50-
#define RTL9300_I2C_MST_CTRL2_DATA_WIDTH_OFS 4
51-
#define RTL9300_I2C_MST_CTRL2_DATA_WIDTH_MASK GENMASK(7, 4)
52-
#define RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_OFS 2
53-
#define RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_MASK GENMASK(3, 2)
54-
#define RTL9300_I2C_MST_CTRL2_SCL_FREQ_OFS 0
55-
#define RTL9300_I2C_MST_CTRL2_SCL_FREQ_MASK GENMASK(1, 0)
5676
#define RTL9300_I2C_MST_DATA_WORD0 0x8
5777
#define RTL9300_I2C_MST_DATA_WORD1 0xc
5878
#define RTL9300_I2C_MST_DATA_WORD2 0x10
5979
#define RTL9300_I2C_MST_DATA_WORD3 0x14
60-
6180
#define RTL9300_I2C_MST_GLB_CTRL 0x384
6281

6382
static int rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len)
6483
{
65-
u32 val, mask;
6684
int ret;
6785

68-
val = len << RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_OFS;
69-
mask = RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_MASK;
70-
71-
ret = regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL2, mask, val);
86+
ret = regmap_field_write(i2c->fields[F_MEM_ADDR_WIDTH], len);
7287
if (ret)
7388
return ret;
7489

75-
val = reg << RTL9300_I2C_MST_CTRL1_MEM_ADDR_OFS;
76-
mask = RTL9300_I2C_MST_CTRL1_MEM_ADDR_MASK;
90+
return regmap_field_write(i2c->fields[F_MEM_ADDR], reg);
91+
}
7792

78-
return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, mask, val);
93+
static int rtl9300_i2c_select_scl(struct rtl9300_i2c *i2c, u8 scl)
94+
{
95+
return regmap_field_write(i2c->fields[F_SCL_SEL], 1);
7996
}
8097

8198
static int rtl9300_i2c_config_io(struct rtl9300_i2c *i2c, u8 sda_pin)
8299
{
100+
struct rtl9300_i2c_drv_data *drv_data;
83101
int ret;
84-
u32 val, mask;
85102

86-
ret = regmap_update_bits(i2c->regmap, RTL9300_I2C_MST_GLB_CTRL, BIT(sda_pin), BIT(sda_pin));
103+
drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->dev);
104+
105+
ret = regmap_field_update_bits(i2c->fields[F_SDA_SEL], BIT(sda_pin), BIT(sda_pin));
87106
if (ret)
88107
return ret;
89108

90-
val = (sda_pin << RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_OFS) |
91-
RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL;
92-
mask = RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_MASK | RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL;
109+
ret = regmap_field_write(i2c->fields[F_SDA_OUT_SEL], sda_pin);
110+
if (ret)
111+
return ret;
93112

94-
return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, mask, val);
113+
return drv_data->select_scl(i2c, 0);
95114
}
96115

97116
static int rtl9300_i2c_config_xfer(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan,
98117
u16 addr, u16 len)
99118
{
100-
u32 val, mask;
119+
int ret;
101120

102121
if (len < 1 || len > 16)
103122
return -EINVAL;
104123

105-
val = chan->bus_freq << RTL9300_I2C_MST_CTRL2_SCL_FREQ_OFS;
106-
mask = RTL9300_I2C_MST_CTRL2_SCL_FREQ_MASK;
107-
108-
val |= addr << RTL9300_I2C_MST_CTRL2_DEV_ADDR_OFS;
109-
mask |= RTL9300_I2C_MST_CTRL2_DEV_ADDR_MASK;
124+
ret = regmap_field_write(i2c->fields[F_SCL_FREQ], chan->bus_freq);
125+
if (ret)
126+
return ret;
110127

111-
val |= ((len - 1) & 0xf) << RTL9300_I2C_MST_CTRL2_DATA_WIDTH_OFS;
112-
mask |= RTL9300_I2C_MST_CTRL2_DATA_WIDTH_MASK;
128+
ret = regmap_field_write(i2c->fields[F_DEV_ADDR], addr);
129+
if (ret)
130+
return ret;
113131

114-
mask |= RTL9300_I2C_MST_CTRL2_RD_MODE;
132+
ret = regmap_field_write(i2c->fields[F_DATA_WIDTH], (len - 1) & 0xf);
133+
if (ret)
134+
return ret;
115135

116-
return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL2, mask, val);
136+
return regmap_field_write(i2c->fields[F_RD_MODE], 0);
117137
}
118138

119139
static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, int len)
@@ -124,8 +144,7 @@ static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, int len)
124144
if (len > 16)
125145
return -EIO;
126146

127-
ret = regmap_bulk_read(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0,
128-
vals, ARRAY_SIZE(vals));
147+
ret = regmap_bulk_read(i2c->regmap, i2c->data_reg, vals, ARRAY_SIZE(vals));
129148
if (ret)
130149
return ret;
131150

@@ -152,52 +171,49 @@ static int rtl9300_i2c_write(struct rtl9300_i2c *i2c, u8 *buf, int len)
152171
vals[reg] |= buf[i] << shift;
153172
}
154173

155-
return regmap_bulk_write(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0,
156-
vals, ARRAY_SIZE(vals));
174+
return regmap_bulk_write(i2c->regmap, i2c->data_reg, vals, ARRAY_SIZE(vals));
157175
}
158176

159177
static int rtl9300_i2c_writel(struct rtl9300_i2c *i2c, u32 data)
160178
{
161-
return regmap_write(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, data);
179+
return regmap_write(i2c->regmap, i2c->data_reg, data);
162180
}
163181

164182
static int rtl9300_i2c_execute_xfer(struct rtl9300_i2c *i2c, char read_write,
165183
int size, union i2c_smbus_data *data, int len)
166184
{
167-
u32 val, mask;
185+
u32 val;
168186
int ret;
169187

170-
val = read_write == I2C_SMBUS_WRITE ? RTL9300_I2C_MST_CTRL1_RWOP : 0;
171-
mask = RTL9300_I2C_MST_CTRL1_RWOP;
172-
173-
val |= RTL9300_I2C_MST_CTRL1_I2C_TRIG;
174-
mask |= RTL9300_I2C_MST_CTRL1_I2C_TRIG;
188+
ret = regmap_field_write(i2c->fields[F_RWOP], read_write == I2C_SMBUS_WRITE);
189+
if (ret)
190+
return ret;
175191

176-
ret = regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, mask, val);
192+
ret = regmap_field_write(i2c->fields[F_I2C_TRIG], 1);
177193
if (ret)
178194
return ret;
179195

180-
ret = regmap_read_poll_timeout(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1,
181-
val, !(val & RTL9300_I2C_MST_CTRL1_I2C_TRIG), 100, 100000);
196+
ret = regmap_field_read_poll_timeout(i2c->fields[F_I2C_TRIG], val, !val, 100, 100000);
182197
if (ret)
183198
return ret;
184199

185-
if (val & RTL9300_I2C_MST_CTRL1_I2C_FAIL)
200+
ret = regmap_field_read(i2c->fields[F_I2C_FAIL], &val);
201+
if (ret)
202+
return ret;
203+
if (val)
186204
return -EIO;
187205

188206
if (read_write == I2C_SMBUS_READ) {
189207
switch (size) {
190208
case I2C_SMBUS_BYTE:
191209
case I2C_SMBUS_BYTE_DATA:
192-
ret = regmap_read(i2c->regmap,
193-
i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, &val);
210+
ret = regmap_read(i2c->regmap, i2c->data_reg, &val);
194211
if (ret)
195212
return ret;
196213
data->byte = val & 0xff;
197214
break;
198215
case I2C_SMBUS_WORD_DATA:
199-
ret = regmap_read(i2c->regmap,
200-
i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, &val);
216+
ret = regmap_read(i2c->regmap, i2c->data_reg, &val);
201217
if (ret)
202218
return ret;
203219
data->word = val & 0xffff;
@@ -355,9 +371,11 @@ static int rtl9300_i2c_probe(struct platform_device *pdev)
355371
{
356372
struct device *dev = &pdev->dev;
357373
struct rtl9300_i2c *i2c;
374+
struct fwnode_handle *child;
375+
struct rtl9300_i2c_drv_data *drv_data;
376+
struct reg_field fields[F_NUM_FIELDS];
358377
u32 clock_freq, sda_pin;
359378
int ret, i = 0;
360-
struct fwnode_handle *child;
361379

362380
i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
363381
if (!i2c)
@@ -376,9 +394,22 @@ static int rtl9300_i2c_probe(struct platform_device *pdev)
376394

377395
platform_set_drvdata(pdev, i2c);
378396

379-
if (device_get_child_node_count(dev) > RTL9300_I2C_MUX_NCHAN)
397+
drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->dev);
398+
if (device_get_child_node_count(dev) > drv_data->max_nchan)
380399
return dev_err_probe(dev, -EINVAL, "Too many channels\n");
381400

401+
i2c->data_reg = i2c->reg_base + drv_data->data_reg;
402+
for (i = 0; i < F_NUM_FIELDS; i++) {
403+
fields[i] = drv_data->field_desc[i].field;
404+
if (drv_data->field_desc[i].scope == REG_SCOPE_MASTER)
405+
fields[i].reg += i2c->reg_base;
406+
}
407+
ret = devm_regmap_field_bulk_alloc(dev, i2c->regmap, i2c->fields,
408+
fields, F_NUM_FIELDS);
409+
if (ret)
410+
return ret;
411+
412+
i = 0;
382413
device_for_each_child_node(dev, child) {
383414
struct rtl9300_i2c_chan *chan = &i2c->chans[i];
384415
struct i2c_adapter *adap = &chan->adap;
@@ -395,7 +426,6 @@ static int rtl9300_i2c_probe(struct platform_device *pdev)
395426
case I2C_MAX_STANDARD_MODE_FREQ:
396427
chan->bus_freq = RTL9300_I2C_STD_FREQ;
397428
break;
398-
399429
case I2C_MAX_FAST_MODE_FREQ:
400430
chan->bus_freq = RTL9300_I2C_FAST_FREQ;
401431
break;
@@ -427,11 +457,37 @@ static int rtl9300_i2c_probe(struct platform_device *pdev)
427457
return 0;
428458
}
429459

460+
#define GLB_REG_FIELD(reg, msb, lsb) \
461+
{ .field = REG_FIELD(reg, msb, lsb), .scope = REG_SCOPE_GLOBAL }
462+
#define MST_REG_FIELD(reg, msb, lsb) \
463+
{ .field = REG_FIELD(reg, msb, lsb), .scope = REG_SCOPE_MASTER }
464+
465+
static const struct rtl9300_i2c_drv_data rtl9300_i2c_drv_data = {
466+
.field_desc = {
467+
[F_MEM_ADDR] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 8, 31),
468+
[F_SDA_OUT_SEL] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 4, 6),
469+
[F_SCL_SEL] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 3, 3),
470+
[F_RWOP] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 2, 2),
471+
[F_I2C_FAIL] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 1, 1),
472+
[F_I2C_TRIG] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 0, 0),
473+
[F_RD_MODE] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 15, 15),
474+
[F_DEV_ADDR] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 8, 14),
475+
[F_DATA_WIDTH] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 4, 7),
476+
[F_MEM_ADDR_WIDTH] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 2, 3),
477+
[F_SCL_FREQ] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 0, 1),
478+
[F_SDA_SEL] = GLB_REG_FIELD(RTL9300_I2C_MST_GLB_CTRL, 0, 7),
479+
},
480+
.select_scl = rtl9300_i2c_select_scl,
481+
.data_reg = RTL9300_I2C_MST_DATA_WORD0,
482+
.max_nchan = RTL9300_I2C_MUX_NCHAN,
483+
};
484+
485+
430486
static const struct of_device_id i2c_rtl9300_dt_ids[] = {
431-
{ .compatible = "realtek,rtl9301-i2c" },
432-
{ .compatible = "realtek,rtl9302b-i2c" },
433-
{ .compatible = "realtek,rtl9302c-i2c" },
434-
{ .compatible = "realtek,rtl9303-i2c" },
487+
{ .compatible = "realtek,rtl9301-i2c", .data = (void *) &rtl9300_i2c_drv_data },
488+
{ .compatible = "realtek,rtl9302b-i2c", .data = (void *) &rtl9300_i2c_drv_data },
489+
{ .compatible = "realtek,rtl9302c-i2c", .data = (void *) &rtl9300_i2c_drv_data },
490+
{ .compatible = "realtek,rtl9303-i2c", .data = (void *) &rtl9300_i2c_drv_data },
435491
{}
436492
};
437493
MODULE_DEVICE_TABLE(of, i2c_rtl9300_dt_ids);

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