Repository navigation
arm: detect Linux userspace ISA extensions - #197
Merged
Merged
Conversation
nihui
force-pushed
the
arm-linux-userspace-isa
branch
from
September 15, 2026 15:46
db5c23c to
6167434
Compare
nihui
force-pushed
the
arm-linux-userspace-isa
branch
from
September 15, 2026 15:58
f26dfc4 to
7090efc
Compare
Use RAX1 for SVE SHA3 and MOVAZ with SM and ZA enabled for SME2.1. Require CP0 WOR after the iWMMXt load to reject NWFPE emulation. Keep smei64i64 as an alias of smei16i64 and reuse adjacent probe results.
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Expand ARM/AArch64 userspace ISA detection using the current Linux ARM HWCAP definitions and Linux's own arm64 hwcap SIGILL selftests as the primary opcode reference.
This keeps ruapu's execute-and-trap design: all new probes are direct
RUAPU_INSTCODE()sequences, with no CPUID/auxv dependency and no new helper-styleruapu_some_xxx()functions.AArch64 additions include:
fp,fphp,lrcpc,ilrcpc,lrcpc3,lse128,lsfe,flagm,flagm2,rng,fpmr,gcs,poe,cssc,cmpbr,hbc,fprcvtfaminmax,lut, FP8 (f8cvt,f8fma,f8dp2,f8dp4,f8mm4,f8mm8), and FP16 matrix/dot (f16mm,f16f32dot,f16f32mm)mopsRDVL, plussve2p2,sve2p3,svef16mm,sveeltperm,sveaes2,svebfscale,sveb16b16,sveb16mm,svelut6, and safersve2p1RDSVL, plus legacy optional features (smei16i64,smef64f64,smei8i32,smef16f32,smeb16f32,smef32f32,smefa64), SME2/2.1/2.2/2.3,smei16i32,smebi32i32,smeb16b16,smef16f16,smeaes,smesbitperm, FP8/LUT/streaming subfeatures,smesfexpa,smesmop4, andsmestmopARM32 additions include:
vfp,fphpasimdbf16,i8mmaes,pmull,sha1,sha2,crc32iwmmxt, using the Linux iWMMXt userspace/lazy-context pathswpis intentionally not exposed: Linux can software-emulate SWP/SWPB after an undefined-instruction trap, so execute-and-trap would conflate kernel emulation with hardware ISA support.Several Linux HWCAPs are intentionally deferred when execute-and-trap cannot identify them reliably or a safe direct probe would require special memory/state handling. Examples include LS64 (requires suitable device/non-cacheable memory), SVE/SME EBF16 behavior flags, FP8 format-only flags, legacy ARM Jazelle/ThumbEE/Crunch, and hint/behavior-only capabilities that are not reliably distinguishable by SIGILL.
README.md,main.c, instruction definitions, andg_ruapu_isa_mapare kept in sync.