STM32F1 core: Implemented changes already made to the GD32F1 core to use F_CPU instead of hard coded values for 72000000 and (F_CPU -1) instead of 71999999 and to replace other hard coded values related to the clock freqency. Also updated the code so that the USB clock was disabled in setup_clock_prescalers to allow it to be changed in that function during initialisation, in case altermative prescaler values for USB are required, e.g. for operation at 48Mhz

Author: rogerclarkmelbourne

STM32F1/cores/maple/libmaple/rcc_f1.c

@@ -104,7 +104,7 @@ void rcc_clk_init(rcc_sysclk_src sysclk_src,
     ASSERT(sysclk_src == RCC_CLKSRC_PLL &&
            pll_src    == RCC_PLLSRC_HSE);
 
-    RCC_BASE->CFGR = pll_src | pll_mul;
+    RCC_BASE->CFGR = pll_src | pll_mul | (0x3<<22);
 
     /* Turn on, and wait for, HSE. */
     rcc_turn_on_clk(RCC_CLK_HSE);
@@ -125,13 +125,13 @@ void rcc_configure_pll(rcc_pll_cfg *pll_cfg) {
     stm32f1_rcc_pll_data *data = pll_cfg->data;
     rcc_pll_multiplier pll_mul = data->pll_mul;
     uint32 cfgr;
-
     /* Check that the PLL is disabled. */
     ASSERT_FAULT(!rcc_is_clk_on(RCC_CLK_PLL));
 
     cfgr = RCC_BASE->CFGR;
     cfgr &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL);
     cfgr |= pll_cfg->pllsrc | pll_mul;
+
     RCC_BASE->CFGR = cfgr;
 }
 
@@ -162,3 +162,12 @@ void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider) {
     };
     rcc_do_set_prescaler(masks, prescaler, divider);
 }
+
+void rcc_clk_disable(rcc_clk_id id) {
+    static __io uint32* enable_regs[] = {
+        [APB1] = &RCC_BASE->APB1ENR,
+        [APB2] = &RCC_BASE->APB2ENR,
+        [AHB] = &RCC_BASE->AHBENR,
+    };
+    rcc_do_clk_disable(enable_regs, id);
+}

STM32F1/libraries/FreeRTOS/utility/FreeRTOSConfig.h

@@ -69,7 +69,7 @@
 #define configUSE_PREEMPTION		1
 #define configUSE_IDLE_HOOK			0
 #define configUSE_TICK_HOOK			0
-#define configCPU_CLOCK_HZ			( ( unsigned long ) 72000000 )
+#define configCPU_CLOCK_HZ			( ( unsigned long ) F_CPU )
 #define configTICK_RATE_HZ			( ( portTickType ) 1000 )
 #define configMAX_PRIORITIES		( ( unsigned portBASE_TYPE ) 5 )
 #define configMINIMAL_STACK_SIZE	( ( unsigned short ) 120 )

STM32F1/libraries/FreeRTOS821/utility/FreeRTOSConfig.h

@@ -85,7 +85,7 @@
 #define configUSE_PREEMPTION		1
 #define configUSE_IDLE_HOOK			0
 #define configUSE_TICK_HOOK			0
-#define configCPU_CLOCK_HZ			( ( unsigned long ) 72000000 )
+#define configCPU_CLOCK_HZ			( ( unsigned long ) F_CPU )
 #define configTICK_RATE_HZ			( ( TickType_t ) 1000 )
 #define configMAX_PRIORITIES		( 5 )
 #define configMINIMAL_STACK_SIZE	( ( unsigned short ) 120 )

STM32F1/libraries/MapleCoOS/utility/OsConfig.h

@@ -42,7 +42,7 @@ Idle task stack size(word).
 /*!< 
 System frequency (Hz).	                 	         
 */    
-#define CFG_CPU_FREQ            (72000000)  
+#define CFG_CPU_FREQ            (F_CPU)  
 
 /*!< 
 systick frequency (Hz).	                         

STM32F1/libraries/MapleCoOS116/utility/OsConfig.h

@@ -70,7 +70,7 @@ Idle task stack size(word).
 /*!< 
 System frequency (Hz).	                 	         
 */    
-#define CFG_CPU_FREQ            (72000000)  
+#define CFG_CPU_FREQ            (F_CPU)  
 
 /*!< 
 systick frequency (Hz).	                         

STM32F1/system/libmaple/include/libmaple/rcc.h

@@ -169,6 +169,12 @@ static inline void rcc_disable_css() {
     RCC_BASE->CR &= ~RCC_CR_CSSON;
 }
 
+/**
+ * @brief Turn off the clock line on a peripheral
+ * @param id Clock ID of the peripheral to turn on.
+ */
+extern void rcc_clk_disable(rcc_clk_id id);
+
 #ifdef __cplusplus
 } // extern "C"
 #endif

STM32F1/system/libmaple/rcc_private.h

@@ -64,4 +64,11 @@ static inline void rcc_do_set_prescaler(const uint32 *masks,
     RCC_BASE->CFGR = cfgr;
 }
 
+static inline void rcc_do_clk_disable(__io uint32** enable_regs,
+                                     rcc_clk_id id) {
+    __io uint32 *enable_reg = enable_regs[rcc_dev_clk(id)];
+    uint8 line_num = rcc_dev_table[id].line_num;
+    bb_peri_set_bit(enable_reg, line_num, 0);
+}
+
 #endif

STM32F1/system/libmaple/stm32f1/include/series/rcc.h

@@ -93,7 +93,7 @@ typedef struct rcc_reg_map {
 #define RCC_CFGR_PLLSRC_BIT             16
 
 #define RCC_CFGR_MCO                    (0x3 << 24)
-#define RCC_CFGR_USBPRE                 (1U << RCC_CFGR_USBPRE_BIT)
+#define RCC_CFGR_USBPRE                 (0x3 << RCC_CFGR_USBPRE_BIT)
 #define RCC_CFGR_PLLMUL                 (0xF << 18)
 #define RCC_CFGR_PLLXTPRE               (1U << RCC_CFGR_PLLXTPRE_BIT)
 #define RCC_CFGR_PLLSRC                 (1U << RCC_CFGR_PLLSRC_BIT)
@@ -525,7 +525,26 @@ typedef enum rcc_ahb_divider {
 } rcc_ahb_divider;
 
 /**
- * @brief Start the low speed internal oscillatior
+ * @brief STM32F1 USB prescaler dividers
+ * @see rcc_set_prescaler()
+ */
+ /*
+ Set and reset by software to control the USB clock prescaler value. The USB clock
+must be 48MHz. These bits can’t be reset if the USB clock is enabled.
+00: (CK_PLL / 1.5) selected
+01: CK_PLL selected
+ */
+ 
+typedef enum rcc_usb_divider {
+    RCC_USB_SYSCLK_DIV_1 = 0x1 << 22,
+    RCC_USB_SYSCLK_DIV_1_5 = 0x0 << 22,
+//GD32 only    RCC_USB_SYSCLK_DIV_2 = 0x3 << 22,
+//GD32 only    RCC_USB_SYSCLK_DIV_2_5 = 0x2 << 22,
+} rcc_usb_divider;
+
+
+/**
+ * @brief Start the low speed internal oscillator
  */
 static inline void rcc_start_lsi(void) {
 	*bb_perip(&RCC_BASE->CSR, RCC_CSR_LSION_BIT) = 1;

STM32F1/system/libmaple/stm32f1/include/series/stm32.h

@@ -221,13 +221,13 @@ extern "C" {
 
 #if STM32_F1_LINE == STM32_F1_LINE_PERFORMANCE
 #    ifndef STM32_PCLK1
-#    define STM32_PCLK1                     36000000U
+#    define STM32_PCLK1                     F_CPU/2
 #    endif
 #    ifndef STM32_PCLK2
-#    define STM32_PCLK2                     72000000U
+#    define STM32_PCLK2                     F_CPU
 #    endif
 #    ifndef STM32_DELAY_US_MULT
-#    define STM32_DELAY_US_MULT             12 /* FIXME: value is incorrect. */
+#		define STM32_DELAY_US_MULT 				(F_CPU / 6000000L)
 #    endif
 #elif STM32_F1_LINE == STM32_F1_LINE_VALUE        /* TODO */
 #    ifndef STM32_PCLK1

STM32F1/variants/generic_stm32f103c/board/board.h

@@ -37,7 +37,7 @@
 #define _BOARD_GENERIC_STM32F103C_H_
 
 #define CYCLES_PER_MICROSECOND    72
-#define SYSTICK_RELOAD_VAL     71999 /* takes a cycle to reload */
+#define SYSTICK_RELOAD_VAL     (F_CPU/1000) - 1 /* takes a cycle to reload */
 
 #define BOARD_NR_USARTS           3
 #define BOARD_USART1_TX_PIN       PA9