Pull requests · ucb-bar/chipyard

Stage Kodiak OPU active-row AutoCounter build

#2395copparihollmann opened

Nov 6, 2026

Connect Firechip CTC to bidirectional F2 streams

#2394iansseijelly opened

Nov 3, 2026

Contributor16 tasks

Adds Ethernet MAC Generator.

#2393milovanovic opened

Oct 26, 2026

Contributor9 of 16 tasks 1.16.0

Move from Conda to Pixi

#2392jimfangx opened

Oct 22, 2026

Member16 tasks 1.16.0

Add Chiplet Router

#2390schwarz-em opened

Oct 12, 2026

Contributor 1.16.0

2

Interval Trace Bridge

#2389iansseijelly opened

Oct 9, 2026

Contributor2 of 16 tasks

2

sdboot: fix the SD card SPI clock (initialization speed, divisor rounding, bus, stale image)

#2386cwssemi opened

Oct 2, 2026

Contributor

2

DO NOT MERGE: Test CI

#2384jimfangx opened

Sep 11, 2026

Member16 tasks

1

fpga/arty: add TinyRocketArtyBScanConfig, JTAG DTM over the FPGA TAP

#2378disdi opened

Sep 3, 2026

4 of 16 tasks

1

Document Verilator's incorrect 'ulimit -c' stack size suggestion

#2377SritejBommaraju opened

Sep 3, 2026

9 of 16 tasks

3

Remove stale references to the deprecated Scala FIRRTL compiler

#2376SritejBommaraju opened

Sep 3, 2026

10 of 16 tasks 1.16.0

2

Draft: Resolve implicit-width-truncation warnings

#2371tynan-jdwk opened

Aug 17, 2026

Contributor2 of 16 tasks

docs: make SKIP_URL_CHECK=1 actually bypass the gh-file-ref URL checks

#2367eastagiletracker opened

Aug 12, 2026

1

fixed submodule added with ssh - while all others with https

#2366rasmus-madsen opened

Aug 7, 2026

6 of 16 tasks

2

Attention accelerator

#2365AlexisHernandez1 opened

Jul 29, 2026

16 tasks

Bump inclusive LLC for sbus-cbus clocking fix

#2364tynan-jdwk opened

Jul 27, 2026

Contributor6 of 16 tasks

firechip: add direct JTAG bridge

#2359tamzidrazzaque opened

Jul 20, 2026

Bump toolchains/riscv-tools/riscv-isa-sim from `9c190a0` to `1280c3c`

#2353dependabot[bot] opened

Jun 22, 2026

Bot

Bump toolchains/riscv-tools/riscv-tests from `0494f95` to `34e6b6d`

#2352dependabot[bot] opened

Jun 22, 2026

Bot

Bump toolchains/riscv-tools/riscv-openocd from `8f59570` to `eb01c63`

#2346dependabot[bot] opened

Jun 3, 2026

Bot

Bump toolchains/riscv-tools/riscv-spike-devices from `887b868` to `9ba9f87`

#2344dependabot[bot] opened

Jun 3, 2026

Bot

Bump toolchains/riscv-tools/riscv-pk from `abadfdc` to `9c61d29`

#2343dependabot[bot] opened

Jun 3, 2026

Bot

Bump actions/checkout from 4 to 6

#2342dependabot[bot] opened

Jun 3, 2026

Bot

Bump softprops/action-gh-release from 2.2.1 to 3.0.0

#2341dependabot[bot] opened

Jun 3, 2026

Bot

Bump dorny/paths-filter from 3 to 4

#2340dependabot[bot] opened

Jun 3, 2026

Bot

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Stage Kodiak OPU active-row AutoCounter build

Connect Firechip CTC to bidirectional F2 streams

Adds Ethernet MAC Generator.

Move from Conda to Pixi

Add Chiplet Router

Interval Trace Bridge

sdboot: fix the SD card SPI clock (initialization speed, divisor rounding, bus, stale image)

DO NOT MERGE: Test CI

fpga/arty: add TinyRocketArtyBScanConfig, JTAG DTM over the FPGA TAP

Document Verilator's incorrect 'ulimit -c' stack size suggestion

Remove stale references to the deprecated Scala FIRRTL compiler

Draft: Resolve implicit-width-truncation warnings

docs: make SKIP_URL_CHECK=1 actually bypass the gh-file-ref URL checks

fixed submodule added with ssh - while all others with https

Attention accelerator

Bump inclusive LLC for sbus-cbus clocking fix

firechip: add direct JTAG bridge

Bump toolchains/riscv-tools/riscv-isa-sim from `9c190a0` to `1280c3c`

Bump toolchains/riscv-tools/riscv-tests from `0494f95` to `34e6b6d`

Bump toolchains/riscv-tools/riscv-openocd from `8f59570` to `eb01c63`

Bump toolchains/riscv-tools/riscv-spike-devices from `887b868` to `9ba9f87`

Bump toolchains/riscv-tools/riscv-pk from `abadfdc` to `9c61d29`

Bump actions/checkout from 4 to 6

Bump softprops/action-gh-release from 2.2.1 to 3.0.0

Bump dorny/paths-filter from 3 to 4