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refactor(platform): separate SoC integration and shared IP drivers - #36
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Move maintained SoC adapters beside hardware facts and shared register engines into private drivers. Preserve static factories, selected CMake compilation contexts and all existing configuration test identities. Close migrated input, SDK-private-header, static-analysis and target-local lifecycle evidence boundaries with executed RED/GREEN regressions. Document the layout in both languages and retain the R01-R48 task ledger. Validation: 136 baseline assemblies have no effective configuration change; 17 focused CTest programs / 267 Google cases pass; full commit gates run on this staged tree. Physical HIL remains not executed.
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| import preflight | ||
| import gpio_phase | ||
| from tools.configure.providers.common import mode_traits | ||
| from tools.configure import can, usb_device, ethernet, timer_advanced, secondary_controllers, preflight, gpio_phase |
| sys.path.insert(0, str(Path(__file__).resolve().parents[2])) | ||
|
|
||
| from tools.configure import kernel, metadata, factory, sdk | ||
| from tools.configure.ir import CpuProfileIR, freeze, thaw |
| except ImportError: | ||
| from providers.common import fail | ||
| from memory import dma_regions | ||
| from tools.configure.providers.common import fail |
| from providers.common import fail | ||
| from memory import dma_regions | ||
| from tools.configure.providers.common import fail | ||
| from tools.configure.memory import dma_regions |
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| self.assertTrue({"vendor", "source_directory", | ||
| "configuration_directory"} <= fields) |
| from providers import common, maintained | ||
| from tools.configure import configure as gate | ||
| from tools.configure import selection | ||
| from tools.configure.providers import common, maintained |
Resolve exact part geometry and selected controller integration from canonical facts and typed resource plans. Colocate reviewed hardware policies with each SoC and keep common generators responsible for shared assembly mechanisms. Separate immutable I2C and UART configuration from BSS runtime state, and move selected cold initialization into concrete SoC functions with retained-failure recovery. Preserve public typed factory interfaces and direct IRQ dispatch. Cover fact admission, input closure, aliases, retained state, standalone Flash geometry, SDK payloads and Runtime boundaries with regression contracts. Update bilingual architecture and porting documentation with measured RAM/Flash costs.
| def selected_preflight(result, *, dma_conditions=None): | ||
| """Cold GPIO/byte-UART profiles keep family-specific banks and SDK hooks.""" | ||
| hook = 'U575' | ||
| gate_register = 'APB2ENR' |
| """Cold GPIO/byte-UART profiles keep family-specific banks and SDK hooks.""" | ||
| hook = 'U575' | ||
| gate_register = 'APB2ENR' | ||
| uart = 'USART1' |
| gate_register = 'APB2ENR' | ||
| uart = 'USART1' | ||
| mux_register = 'CCIPR1' | ||
| mux = 'RCC_CCIPR1_USART1SEL' |
| if region["id"] == "sram") | ||
| memory["size"] = 65536 | ||
| source = bindings.emit(result)[1] | ||
| self.assertTrue("{ 0x20000000u, 65536u," in source) |
VectorQiu
changed the title
| overlap(config, sizeof(*config), (const void*)config->reset, | ||
| sizeof(*config->reset))) | ||
| return NX_ERROR_INVALID; | ||
| p->config = config; |
| state->uart.receive = &state->receive; | ||
| state->uart.rx_capacity = 0U; | ||
| config.profile = NX_UART_RX_BLOCKS; | ||
| config.receive = &state->receive; |
| DuplexState state = {}, other = {}; | ||
| ConfigureDuplex(&state); | ||
| state.uart.receive = &other.receive; | ||
| config.receive = &other.receive; |
| return config == NULL || config->profile != NX_UART_RX_BLOCKS || | ||
| (config->receive->stream == NULL && !config->receive->filling); | ||
| } | ||
| static nx_result_t initialize(nx_uart_v1_dma_state_t* s, |
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Hardware configuration policy and reusable peripheral implementations were distributed across generic tools and SoC folders. This change places exact chip policy in
soc/<vendor>/<family>/configure/and reviewed shared implementations indrivers/<class>/<reviewed-ip>/. Cortex-M mechanisms remain inarch/arm/cortex_m; CMake remains the source graph, and TOML still resolves through the typed IR into a static factory.All seven MCU Flash geometries now derive from canonical SoC facts. The typed controller integration record references existing resource, IRQ, DMA, clock and pin records; selected F407 SPI and secondary-controller consumers use those records. SoC hooks own family policy. Selected G474/H743/U575 I2C V2 and F103/GD303 UART DMA implementations separate readonly configuration from mutable state while preserving borrowing, retained failure, shared operations and direct IRQ dispatch. SDK closure, diagnostics, bilingual guidance and architecture diagrams follow these boundaries.
Evidence is bound to clean platform commit
92e669233957a2e450a528394e8f4dd0794c7049, tree6e38d4c43d59330a0a9a9b7cac21f591d9c2719f:runningreport and incomplete tidy evidence. Source, dependencies and recorded tool identities were checked after restart.executed_passed, clean equal source before/after and complete 865-context runs for both tidy and cppcheck. The exact original 159 stages are covered by A90 + B69. Its final report SHA-256 isf8ecf185eadbef7e33d7a667366da7de34241ce243a5d417b5b453ae3bb99694. The segments are not represented as one uninterrupted passing run; no successful test report substitutes for a new execution.0f15022e4d5f5c51991b134d0b9d6082dcf88de9: completelocal_ci --scope all, 98 commands, 80 tool tests, 15 Native CTest entries / 69 Google cases, 16 ARM presets, and the installed-SDK Native consumer. These counts overlap ordinary hook coverage and are not added together. The pin update is nexus-examples#15.7f89e8ec33a543e150e7165a3e4252aa11a96d62fe5d3187a9b0d4791aa618b4. It is a software-qualified candidate; physical status remainsnot_executed.At the recorded GitHub observation, all 36 platform check runs were successful. Fourteen CodeQL comment threads remain unresolved. Their existing read-only review found no confirmed production dangling binding or dead UART initialization, and retained nonblocking cleanup findings; this is not a claim that every alert is a false positive or that the source has zero alerts.
Physical HIL remains
not_executed. Native models and ARM linking/resource checks do not establish board wiring, timing, electrical behavior or power-loss safety.Recoverable delivery artifacts are retained in the shared workspace:
nexus-examples/build/platform-candidate-92e669233957/completion-2/candidate-portable.jsonidentifies the portable candidate; the R42/R45 compact archive issdk-examples-validation-evidence.tar.gz(SHA-2562d8ef5bf109ddb5c1d079c9c6b9b0ca0de9768649c065e63192bc7bd72f09510). Exact per-configuration costs are innexus/build/quality/soc-ip-final-p-92e669233957/final-cost-summary.json. These paths describe local retained artifacts, not GitHub-hosted release assets.